Pad arrangement for a semiconductor device

Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure

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257203, 257208, H01L 2302

Patent

active

053471458

ABSTRACT:
A semiconductor device comprises a rectangular semiconductor chip provided with an integrated circuit, and a plurality of voltage stress examination pads formed on the semiconductor chip for applying stress examination voltage to the integrated circuit, and having the same function, wherein the voltage stress examination pads are provided on opposite sides of the semiconductor chip.

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"Protecting Si Wafers Against Damage During Testing", IBM Technical Disclosure Bulletin, vol. 32, No. 4A, Sep. 1989, p. 121.
Pearson, "Masterplan (A Simplified Method of Design)", Proceedings of the 1st International Conference on SemiCustom ICs, Nov. 1981, pp. 201-213.

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