Packing density for flash memories

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

257315, H01L 29788

Patent

active

058922571

ABSTRACT:
Improved packing density as well as improved performance and manufacturing yield is achieved in an electrically programmable memory by confining floating gate structures between isolation structures covered with a thin nitride layer. The confinement of the floating gate is achieved by planarization, preferably with a self-limiting chemical/mechanical polishing process, to the surface of the nitride layer covering the isolation structures. Gate oxide and control electrode connections can then be formed on a substantially planar surface without compromising the quality of the gate oxide or breakdown voltage the device must withstand for programming. Since severe topology is avoided over which these connections are formed, improved formation of low resistance connections, possibly including metal connections, are possible and allow scaling of transistors of the memory cells to be scaled to sizes not previously possible.

REFERENCES:
patent: 4597060 (1986-06-01), Mitchell et al.
patent: 4651406 (1987-03-01), Shimizu et al.
patent: 4663645 (1987-05-01), Komori et al.
patent: 4833514 (1989-05-01), Esquivel et al.
patent: 4905062 (1990-02-01), Esquivel et al.
patent: 4944836 (1990-07-01), Beyer et al.
patent: 4997781 (1991-03-01), Tigelaar
patent: 5032881 (1991-07-01), Sardo et al.
patent: 5047362 (1991-09-01), Bergemont
patent: 5120670 (1992-06-01), Bergmont
patent: 5143860 (1992-09-01), Mitchell et al.
patent: 5150178 (1992-09-01), Mori
patent: 5179427 (1993-01-01), Nakayama et al.
patent: 5324972 (1994-06-01), Takebuchi et al.
patent: 5338956 (1994-08-01), Nakamura
patent: 5401992 (1995-03-01), Ono
patent: 5402372 (1995-03-01), Bergemont
patent: 5541130 (1996-07-01), Ogura et al.
Y.S. Hisamune, et al.. "3.6 .mu.m.sup.2 Memory Cell Structure for 16MB EPROMS", 1989, pp. 583-586.
"A New Self-Aligned Planar Array Cell for Ultra High Density EPROMS"; A. T. Mitchell et al.; Texas Instruments Incorporation; IEEE 1987; pp. 548-551.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Packing density for flash memories does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Packing density for flash memories, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Packing density for flash memories will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-1373834

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.