Packet switch with multiple addressable components

Details Packet switch with multiple addressable components Packet switch with multiple addressable components

2008-04-08

2008-04-08

Lee, Christopher E. (Department: 2111)

Electrical computers and digital data processing systems: input/

Intrasystem connection

System configuring

C710S316000, C709S238000, C370S392000

Reexamination Certificate

active

11129600

ABSTRACT:
An integrated circuit on which are implemented a number of devices that conform to the Rapidio network architecture. Included in the integrated circuit are two addressed RapidIO devices and switching devices which provide 24 switching ports. The devices have a packet receiving side and a packet transmitting side; the packet receiving side of each of the devices is connected by 128-bit wide paths termed poles its own packet transmitting side and each of the other transmitting sides. Features of the integrated circuit include centralized multicasting and configuration control for all of the devices on the integrated circuit, provisions for having more than one address in a RapidIO device, techniques for defining the address space routed by a routing table, techniques for managing congestion, and advanced buffer management techniques.

REFERENCES:
patent: 6181679 (2001-01-01), Ashton et al.
patent: 6208647 (2001-03-01), Deng et al.
patent: 6272582 (2001-08-01), Streitenberger et al.
patent: 6496505 (2002-12-01), La Porta et al.
patent: 6662257 (2003-12-01), Caruk et al.
patent: 6823386 (2004-11-01), Crump et al.
patent: 6823418 (2004-11-01), Langendorf et al.
patent: 6922749 (2005-07-01), Gil et al.
patent: 6928529 (2005-08-01), Shinomiya
patent: 6946948 (2005-09-01), McCormack et al.
patent: 6947398 (2005-09-01), Ahmed et al.
patent: 7023829 (2006-04-01), Holmquist et al.
patent: 7035286 (2006-04-01), Tzeng
patent: 7039749 (2006-05-01), Harris et al.
patent: 7043569 (2006-05-01), Chou et al.
patent: 7065040 (2006-06-01), Nagamine
patent: 7139840 (2006-11-01), O'Toole
patent: 2003/0154341 (2003-08-01), Asaro et al.
patent: 2004/0059957 (2004-03-01), Menasce et al.
patent: 2004/0064290 (2004-04-01), Cabral et al.
patent: 2005/0135337 (2005-06-01), Nabeta et al.
patent: 2006/0146812 (2006-07-01), Farr et al.
patent: 2006/0174052 (2006-08-01), Kondo et al.

Affiliated with

Also associated with

Rating

Packet switch with multiple addressable components does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Packet switch with multiple addressable components, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Packet switch with multiple addressable components will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3957266