Packet receiving device

Details Packet receiving device Packet receiving device

1995-09-06

1998-07-14

Chin, Wellington

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

370503, 375355, H03D 324

Patent

active

057815992

ABSTRACT:
An apparatus for receiving and decoding a packet of a multiplexed bit stream whose data is coded in a predetermined format, includes a temporary storage memory for compensating for the difference between the timing of the received packet and the read-in timing of the coded data by a decoder, counters and a comparison circuit for producing a clock signal which serves as a reference for operating the decoder on the basis of a reference signal in the predetermined format, and a calculation circuit for calculating the position of the reference signal using a time which is periodically added to the packet.

REFERENCES:
patent: 5566174 (1996-10-01), Sato et al.
patent: 5633871 (1997-05-01), Bloks
patent: 5640392 (1997-06-01), Hayashi
IEEE Standards Draft, "Annex C. Cable Operation and Implementation Examples (informative)", In High Performance Serial Bus, P1394/Draft 6.4v0, Oct. 14, 1993, (IEEE).

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