Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Reexamination Certificate
2006-09-07
2009-12-15
Chace, Christian P (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
C711S147000, C711S148000, C711S149000, C711S150000, C711S202000, C370S395400, C370S395410, C370S395420, C370S375000, C370S376000, C709S214000, C709S215000, C709S240000
Reexamination Certificate
active
07634622
ABSTRACT:
A shared memory stores packets for a packet processor. The shared memory is arranged into banks that are word-interleaved. All banks may be accessed in parallel during each time-slot by different requesters. A staggered round-robin arbiter connects requesters to banks in a parallel fashion. Requestor inputs to the arbiter are staggered to allow access to different banks in a sequential order over successive time-slots. Multi-processor tribes have many processors that generate random requests to the shared memory. A slot scheduler arranges these random requests into a stream of sequential requests that are synchronized to the staggered round-robin arbiter. A packet interface requestor stores incoming packets from an external network into the shared memory. The packet's offset within pages of the shared memory is determined by the first available bank that the packet can be written to, eliminating delays in storing incoming packets and spreading storage of frequently-accessed fields.
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Huynh Jeffrey
Musoll Enrique
Nemirovsky Mario
Auvinen Stuart T.
Chace Christian P
Consentry Networks, Inc.
gPatent LLC
Thammavong Prasith
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