Packet processor memory interface with late order binding

Details Packet processor memory interface with late order binding Packet processor memory interface with late order binding

2007-10-31

2009-02-24

Elmore, Stephen C (Department: 2185)

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

C711S158000, C711S221000, C370S394000, C709S216000, C709S229000, C712S218000, C712S225000

Reexamination Certificate

active

07496721

ABSTRACT:
A mechanism receives memory reads and writes from a packet processing engine, each memory access having an associated packet identifier or sequence number. The mechanism is placed between the packet processing engine and a memory system such that write data is buffered and information based upon both reads and writes is recorded. Information is maintained allowing the detection of memory conflicts. Both a strict and alternate packet ordering are evaluated, such that the semantic ordering of packets is delayed until necessary to ensure that a consistent order exists. Such a late order binding mechanism is used to allow packets to be defined in any order so long as they obey a consistent order, thereby reducing the number of packet restarts and increasing overall efficiency.

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