Packet processor memory interface

Details Packet processor memory interface Packet processor memory interface

2006-09-12

2006-09-12

Elmore, Stephen C. (Department: 2185)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S154000, C711S158000, C711S221000, C370S394000, C709S216000, C709S229000, C712S218000, C712S225000

Reexamination Certificate

active

07107402

ABSTRACT:
A mechanism processes memory reads and writes in a packet processor. Each memory access has an associated sequence number and information is maintained allowing the detection of memory conflicts. The mechanism is placed between a processing element and a memory system such that write data is buffered and both reads and writes are recorded. When a memory conflict is detected, based on a strict or alternate ordering model, a restart signal is generated and the entries for the associated sequence number are flushed. When the work associated with a sequence number has completed, a signal is made so that associated write data can be sent to the memory system and the entries for that sequence number can be flushed.

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