Packet processor memory conflict prediction

Details Packet processor memory conflict prediction Packet processor memory conflict prediction

2006-09-11

2008-10-21

Elmore, Stephen C (Department: 2185)

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

C711S158000, C711S221000, C370S394000, C709S216000, C709S229000

Reexamination Certificate

active

07441088

ABSTRACT:
A mechanism receives memory reads and writes from a packet processing engine, each memory access having an associated packet identifier. Upon receiving a memory read, conflict prediction logic determines if a future conflict with a memory write is likely, and if so the processing of the memory read is delayed. After the write to which the read depends is received, the delayed memory read is allowed to complete. Such a delayed read mechanism can reduce or eliminate work discarded due to memory conflicts detected after the fact, while preserving the sequential semantics of the packet processor. The conflict prediction logic can be used in conjunction with conflict detection in which write data is buffered and information associated with both reads and writes is recorded.

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