Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis
Reexamination Certificate
2007-02-20
2007-02-20
Lee, Thomas (Department: 2115)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
C713S501000, C713S502000
Reexamination Certificate
active
10725784
ABSTRACT:
A method and system are provided for processing data packets at a data-transfer network node. The method and system include determining a length of time that a packet has been buffered at the node by associating a timer with each data packet received and buffered in the node's central queue. The central queue subsequently reads the associated timer to determine a length of time that a data packet has been buffered prior to the data packet being transmitted by the node. If a packet has been buffered too long, then the queue discards the packet. Otherwise, the queue permits transmission of the packet. The amount of circuitry in the switching node's central queue is reduced by locating the packet timers in timer logic external to the queue.
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Garmire Derrick L.
Rider Scot H.
Campbell John E.
Cribbs Malcolm
Heslin Rothenberg Farley & & Mesiti P.C.
Lee Thomas
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