Packet memory system

Details Packet memory system Packet memory system

2005-08-02

2005-08-02

Kizou, Hassan (Department: 2662)

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

C370S412000, C370S428000, C710S308000, C711S105000, C711S154000

Reexamination Certificate

active

06925086

ABSTRACT:
A packet memory system is provided. The packet memory system includes a memory cell array for storing a predefined number of packets. Each packet includes a predetermined number of segments. Each of the segments defines a starting point of a memory access. A packet decoder coupled to the memory cell array receives packet select inputs for selecting a packet. A segment decoder coupled to the memory cell array receives segment select inputs for selecting a segment. A data flow multiplexer is coupled to the memory cell array for transferring data between a data bus and the memory cell array. Command and mode registers receive command, read/write (R/W) and chip select (CS) inputs for opening a packet. Responsive to an opened packet, the packet select inputs provide a length for the memory access. Each of the segments has a preprogrammed length. Also each of the segments can be defined for a cache line.

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