Packet buffer memory with integrated...

Details Packet buffer memory with integrated... Packet buffer memory with integrated...

2005-08-02

2005-08-02

Nguyen, Hiep T. (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Memory configuring

Reexamination Certificate

active

06925544

ABSTRACT:
A buffer memory with a memory allocation and de-allocation circuit. The buffer memory has an address space divided into address blocks and a memory address space divided into memory blocks. The circuit, in response to an allocation request for an allocation of a certain size buffer, allocates sufficient address blocks and memory blocks for the buffer. The circuit, in response to a de-allocation request to de-allocate a certain size of memory, de-allocates whole unused address blocks and memory blocks.

REFERENCES:
patent: 6212613 (2001-04-01), Belair
patent: 6279080 (2001-08-01), DeRoo
patent: 6286088 (2001-09-01), Campbell et al.

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