Packaging substrate comprising staggered vias

Details Packaging substrate comprising staggered vias Packaging substrate comprising staggered vias

2001-01-31

2003-03-25

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Lead frame

On insulating carrier other than a printed circuit board

C257S203000, C257S676000, C257S786000

Reexamination Certificate

active

06538307

ABSTRACT:

TECHNICAL FIELD
The present invention relates to semiconductor packaging technology. The present invention has particular applicability to semiconductor packages containing a substrate comprising fan-out circuitry electrically interconnected by vias.
BACKGROUND ART
Ongoing advances in solid-state electronic devices impose continuous demands for integrated circuit devices with increased functionality, density, and performance. In response, multi-chip modules have evolved comprising a printed circuit board substrate to which a series of separate components are directly attached. Multi-chip devices advantageously increase circuit density with attendant improvements in signal propagation speed and overall device weight.
Integrated circuit devices are typically electronically packaged by mounting one or more chips to a substrate, e.g., an alumna circuitize substrate or an organic substrate, sometime referred to as a chip carrier. Wire bonds or bumps are employed to electrically connect input/output (IO) contact pads on each chip to corresponding fan-out circuitry on the circuitized chip carrier substrate. The resulting chip carrier is then typically mounted on a printed circuit board (PCB) and, employing circuitry on the PCB, electrically coupled to other such chip carriers and/or other electronic components mounted on the PCB.
Conventional organic circuitized substrates contain two or more layers of fan-out circuitry on two or more organic layers. Such layers of fan-out circuitry are electrically interconnected by mechanically drilled holes known as vias which are plated and/or filled with electrically conductive material, e.g., copper. Some of the holes extend from the layers of fan-out circuitry to respective lands on the chip carrier substrates, on which are mounted solder balls forming a grid array, thereby generating the expression “ball grid array”. The solder balls are mechanically and electrically connected to corresponding solderable contact pads on the PCB.
Unfortunately, the mechanically drilled holes or vias electrically interconnecting the layers of fan-out circuitry have very large diameters, requiring the spacing between the fan-out wires to be relatively large, thereby limiting the number of chip I/O pads which can be accommodated by the multilayered substrates. Moreover, conventional practices comprise forming the vias in aligned rows. For example, adverting to
FIG. 1
, an upper surface of chip carrier substrate
10
comprises two rows of substantially aligned vias, one row of vias substantially aligned with via
11
and another row of vias aligned with via
12
. Circuitry lines from such vias are illustrated by reference numeral
13
with respect to vias aligned with via
11
and reference numeral
14
with respect to vias aligned with via
12
. The bottom surface of chip carrier substrate
10
is schematically illustrated in FIG.
2
and comprises vias
11
and
12
, solder balls
22
, and circuitry wiring
23
. Such chip carrier substrates have been found to cause failures during various assembling stages, such as die-attaching a semiconductor chip to the upper surface of the substrate and molding to encapsulate the semiconductor die on the substrate with a molding compound.
Accordingly, there exists a need for chip carrier substrates exhibiting high strength and rigidity for use in semiconductor packaging.
SUMMARY OF THE INVENTION
An advantage of the present invention is a chip carrier substrate exhibiting improved strength and rigidity.
Additional advantages and features of the present invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a substrate for attaching a semiconductor die to a printed circuit board, the substrate comprising: an upper surface and a lower surface; and vias extending through the substrate between the upper and lower surfaces, wherein the vias are offset from one another such that less than 20% of the vias are aligned.
Embodiments of the present invention comprise substrates having at least 48 vias interconnecting fan-out circuitry. Embodiments of the present invention further include a circuit assembly comprising at least one semiconductor die attached to a printed circuit board by means of a substrate in accordance with the present invention.


REFERENCES:
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patent: 5583376 (1996-12-01), Sickler et al.
patent: 5686699 (1997-11-01), Chu et al.
patent: 6150193 (2000-11-01), Glenn

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