Packaging substrate and manufacturing method thereof,...

Details Packaging substrate and manufacturing method thereof,... Packaging substrate and manufacturing method thereof,...

2006-03-21

2006-03-21

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Responsive to non-electrical signal

Physical deformation

C257S254000, C257S482000, C257S777000, C257S778000

Reexamination Certificate

active

07015556

ABSTRACT:
A basic portion layer21of a substrate electrode12aconnected to a projecting electrode13electrically and mechanically on a substrate member of ceramics. The substrate member on which the basic portion layer21is formed is subjected to sintering. A surface of the basic portion layer21in the sintered substrate member is polished. On the polished basic portion layer21, the plating layers22, 23are formed, so that surface roughness of the substrate electrode12amay be, for example, not larger than 0.1 μmRMS. Accordingly, junction strength of an integrated circuit element mounted on a packaging substrate by a flip-chip method can be improved.

REFERENCES:
patent: 5901041 (1999-05-01), Davies et al.
patent: 6392294 (2002-05-01), Yamaguchi
patent: 6437439 (2002-08-01), Shimoe
patent: 2004/0108560 (2004-06-01), Taga

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