Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Reexamination Certificate
2002-01-07
2002-12-10
Dang, Trung (Department: 2812)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
C438S110000, C438S113000
Reexamination Certificate
active
06492196
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a packaging method for the wafer level IC device, especially to a kind of packaging method for IC device just by applying the traditional wafer process and the BGA packaging technology completely without any additional special wafer process to fulfill the merits of smaller size and thinner thickness in the same packaging volume as that of the IC device produced by the Wafer Level Packaging technology.
2. Background of the Invention
For packaging an IC device, except a traditional lead frame is needed as signal connection interface between the IC chip and the outside such as circuit board or motherboard, another kind of electric connection medium with metal ball (e.g. solder ball) such as common BGA is also available. However, for both the lead frame package of prior arts or the BGA package, they all have the shortcoming that the size of the packaging device is larger relatively. Because their package/chip ratio is at least larger than 1.6, it causes a lot of waste on space, and for the electronic industry requiring fineness, it cannot fulfill the requirement of micronization trend.
Accordingly, the semiconductor industry now has developed a so-called “Chip Scale Package, CSP” technique to make the package/chip ratio of the IC device lower than 1.2. Further, relative industry combines the package process directly with wafer process to create a so-called “Wafer Level IC Device Packaging Technique”, by which the process produces IC package device, size of which is almost same as that of the original chip. Therefore, it promotes the package/chip ratio close to 1 for extremely avoiding the waste of space possibly caused by the traditional package.
Please refer to
FIG. 1
, which shows a wafer level IC packaging device
1
. Plural ICs (not shown in the figure) that are belonged to the front end of semiconductor process and can be existed independently have already formed. For the active side of the wafer
11
of the wafer level IC packaging device
1
, on which there are mainly formed: patterned metal layer
13
, several pads
16
(A
1
pad, in ordinary), several metal posts
17
(copper posts, in general), resin layers
12
a,
12
b,
and solder ball pad
12
b
that is extended from the IC of the wafer
11
and is applied for welding solder ball
15
. Finally, the solder ball
15
of the wafer level IC packaging device
1
is welded onto a circuit board (commonly known as SMT process, or called ┌ on board ┘ step, which are not shown in the figures).
However, the wafer level IC packaging device
1
is cut entirely to make the wafer
11
separated into several ICs that each one is independently existent. Before the wafer
11
being cut, it will be cured through the step of appropriate bake. At this time, since the coefficient of thermal expansion (abbreviated as CTE) of the resin layer
12
made as buffer layer has some level of difference from that of the wafer
11
after all, so the wafer
11
will be deformed due to the excess stress caused by the differences of expansion situation among several kinds of materials during baking process. Even more seriously, the wafer
11
will be incurred the situations of break and damage to cause the yield of product unable to be promoted effectively.
However, in the common semiconductor industry, when the wafer level IC packaging device
1
is welded onto the circuit board (SMT process), since the coefficient of thermal expansion of the buffer layer is different from that of the circuit board, so the wafer
1
is incurred damaging situation. In order to increase the yield of product, they make their efforts on the design of the buffer. However, they do not know that the wafer
11
still will be incurred the situation of damage even in the baking process at the front end. When the size of wafer is developed from 8 inch to 12 inch, because the number of designed chip is increased greatly, this kind of damaging situation is further serious. According to this, the invention specially provides an innovative packaging process of the wafer level IC device for solving aforementioned problem thoroughly.
SUMMARY OF THE INVENTION
Thus, the main object of the invention is to provide a packaging process for a wafer level IC device. During the wafer being baked, the invention will prevent it from deformation caused by the different stresses incurred from the wafer due to the coefficient of thermal expansion of the buffer layer being somewhat different from that of the wafer. The invention can raise the yield of product effectively, however, without relatively increasing the cost and needed technology of package.
A further object of the invention is to provide a packaging method for a wafer level IC device. Since the invention processes pre-cut before bake, so a gap is created between each two adjacent ICs without existence of any buffer layer. Therefore, when a complete bake is under processing, since a pre-remained space can be provided for the thermal expansion of the buffer layer, so the stress subjected by the wafer during thermal expansion can be reduced and the completeness of the wafer is remained.
To reach above-mentioned objects, a preferable embodiment of the packaging process of the wafer level IC device according to the invention is comprised of following steps:
a. Device preparation: a wafer produced from common semiconductor process is prepared, wherein plural chips capable of independent existence have already formed on one active side of the wafer by the semiconductor process. Each chip all has its own IC action independently. There is patterned metal layer formed on each independent IC, on which a pad is also arranged for electric connection point. Further, a buffer layer is coated on the wafer.
b. Pre-cure step: the buffer layer has not completely hardened yet for the time being by baking with appropriate temperature and just has reached a stable condition sufficiently.
c. Pre-cut step: a cut is made at the position of the buffer corresponding to the boundary of each IC device to make a gap existed between each two adjacent IC devices without containing any buffer layer.
d. Post-cure step: the buffer layer is baked completely to make itself hardened completely with appropriate temperature.
e. Metal ball implant: plural metal balls are implanted for coupling with the solder ball pads on the side surface of the buffer layer that is far away from the wafer.
f. Singulation: the wafer together with the buffer layer are under singulation process to make the plural ICs (chips) separated from each other to become IC device that each can act independently.
Wherein, in the mean time, since the invention has completed the pre-cut before being completely hardened to create a gap existed between each two adjacent IC devices without containing any buffer layer, so when the complete bake is under process, due to the pre-remaining space being available for the buffer layer for thermal expansion, the stress caused by the thermal expansion and subjected by the wafer can be reduced and the completeness of the wafer is remained.
REFERENCES:
patent: 6235552 (2001-05-01), Kwon et al.
patent: 6376279 (2002-04-01), Kwon et al.
patent: 6379999 (2002-04-01), Tanabe
patent: 6387795 (2002-05-01), Shao
patent: 6413799 (2002-07-01), Lam
Dang Trung
PICTA Technology Inc.
Troxell Law Office PLLC
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