Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Portion of housing of specific materials
Reexamination Certificate
2000-06-02
2001-09-18
Clark, Sheila V. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Portion of housing of specific materials
C257S678000, C438S125000
Reexamination Certificate
active
06291882
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a packaging process and structure of an electronic device, and more particularly to a packaging process and structure of an electronic device of an IC (integrated circuit) chip.
2. Description of Related Art
In IC industry, IC package is used for providing the chip with a medium of electrical connection to a PCB (printed circuit board) or to other appropriate devices. In addition, the package also provides the chip a protection from being damaged or short-circuit. And the packaging process is the last process in making the IC products. The IC circuit is generally encapsulated in a package and is then bonded to the PCB or other substrates.
During the packaging process, a two-piece molding equipment is normally employed and a molding compound is generally used to perform encapsulating process for the electronic devices such as IC chip. A chip-carrying substrate is placed into the cavity of a mold, then the molding compound is introduced into the cavity through the mold runner of the mold to encapsulate the chip, afterward, the mold is separated from the package after the molding compound is cured. At this moment, however, since the package is still connected to the molding compound that is cured and is positioned in the mold runner, a degating process is then performed to remove the excess portion so as to accomplish the fabrication of an electronic package.
However, since there are bonding forces existed between the substrate and the molding compound that is positioned in the mold runner, while performing the degating process to remove the excess portion of the molding compound, the substrate will be twisted. In turn, the solder mask on the substrate is impaired, the conductive trace is cracked, and delamination occurs between the molding compound, solder mask, conductive trace, chip, and the substrate, consequently, gaps are generated. Subsequently, moisture penetrates into the gaps which results in the moisture expansion due to the heat to generate the “Popcorn Effect” that eventually damages the package.
Shown in
FIG. 1
is a top view of a package substrate according to the prior art presented in 1994 by Amkor Company and Anam Company with U.S. Pat. No. 5,635,671. A Degating Region
102
made of Gold (Au) or Palladium (Pd) is formed on the mold runner
104
of the substrate. The width of the Degating Region
102
is greater
15
than that of the mold runner
104
. Since the bondability of the molding compound to the gold Degating Region
102
is smaller than the bondability of the molding compound to the substrate
100
, the package structure will not be damaged when it comes to removing the excess molding compound in the mold runner. But the gold Degating Region
102
occupies the substrate area available for the circuit pattern, besides, the fabrication of the gold Degating Region
102
will increase the manufacturing cost of the package.
Shown in
FIG. 2
is an isometric view of a schematic drawing showing the process of removing the excess molding compound according to the prior art presented in 1991 by Motorola Company with U.S. Pat. No. 5,542,171. As shown in the
FIG. 2
, a sputter etching process is performed to a substrate
200
in order to enhance the bondability between the molding compound and the substrate in the subsequent process. Then a contamination process is performed that a coating layer
206
of permanent marking ink or polymer is applied on the contact area between the substrate
200
and a gate
204
through which the mold runner
210
is connected to the semiconductor chip
202
. The coating layer
206
is applied for reducing the bondability between the molding compound and the substrate such that the package structure will not be damaged when it comes to removing the excess molding compound in the mold runner. But the above-mentioned coating process by using the permanent marking ink or polymer is complicated and difficult. The method not only increases the manufacturing cost but also has the concern of damaging the quality of the products.
SUMMARY OF THE INVENTION
It is therefore an objective of the present invention to provide a packaging process and structure to form a hydrophobic Fluorine-containing layer in a novel region on the packaging substrate without affecting the available circuit pattern area on the substrate. This layer can lower the bondability between the substrate and the molding compound positioned in the mold runner. The forming of the layer can protect the package from being damaged during the degating process since the bondability between the hydrophobic Fluorine-containing layer and the molding compound is weaker than the bondability between the molding compound and the substrate. It can also restrain the moisture from penetrating into the package to generate popcorn effect.
In order to attain the foregoing objectives, the present invention presents a packaging process and structure of electronic device. It provides first a substrate having a carrying surface and a mounting surface wherein the carrying surface is divided into a device disposing region and a device peripheral region. Then a hydrophobic Fluorine-containing layer is formed in the device peripheral region of the substrate. Subsequently, an electronic device is attached in the device disposing region and is electrically connected to the substrate. Then, a molding compound is employed to encapsulate the electronic device. The bondability between the hydrophobic Fluorine-containing layer and the molding compound is weaker than the bondability between the molding compound and the substrate. Finally, a degating process is performed to remove the excess molding compound positioned at the hydrophobic Fluorine-containing layer to accomplish the packaging process of the electronic device.
Additionally, in order to attain the foregoing objectives, the present invention provides also a substrate having a carrying surface, a hydrophobic Fluorine-containing layer, an electronic device, and a molding compound. The carrying surface has a device disposing region and a device peripheral region. The hydrophobic Fluorine-containing layer is positioned in the device peripheral region to cover a portion of the substrate. The electronic device is attached in the device disposing region and electrically connected to the substrate. And the molding compound is disposed in the device disposing region to encapsulate the electronic device wherein the bondability between the hydrophobic Fluorine-containing layer and the molding compound is weaker than the bondability between the molding compound and the substrate and/or the electronic device.
REFERENCES:
patent: 4675094 (1987-06-01), Kaminaga et al.
patent: 5215643 (1993-06-01), Kusanagi et al.
patent: 5296122 (1994-03-01), Katsube et al.
patent: 5542171 (1996-08-01), Freyman et al.
patent: 5635671 (1997-06-01), Tuskey et al.
patent: 5846708 (1998-12-01), Hollis et al.
patent: 6087000 (2000-07-01), Girgis et al.
patent: 6193077 (2001-02-01), Withan et al.
Clark Sheila V.
Huang Jiawei
J. C. Patents
Siliconware Precision Industries Co., Letd.
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