Packaging methods for imager devices

Details Packaging methods for imager devices Packaging methods for imager devices

2011-04-05

2011-04-05

Richards, N Drew (Department: 2895)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S065000, C257S294000, C257S621000, C257S680000, C257SE31127

Reexamination Certificate

active

07919410

ABSTRACT:
An imager device is disclosed which includes at least one photosensitive element positioned on a front surface of a substrate and a conductive structure extending at least partially through an opening defined in the substrate to conductively couple to an electrical contact or bond pad on the front surface. An insulating material of a conductive laminate film and/or a mold compound material is positioned within the opening between at least a portion of the conductive structure and the substrate. Also disclosed is a device that comprises a substrate and a plurality of openings in the substrate, wherein each of the openings is adapted to be positioned above an imager device when the substrate is positioned above and secured to an imager substrate. A method of forming an imager device is also disclosed.

REFERENCES:
patent: 2004/0137701 (2004-07-01), Takao
patent: 2004/0188819 (2004-09-01), Farnworth et al.
patent: 2005/0116138 (2005-06-01), Hanada et al.
patent: 2005/0181540 (2005-08-01), Farnworth et al.
patent: 2005/0285154 (2005-12-01), Akram et al.
patent: 2005/0287783 (2005-12-01), Kirby et al.
patent: 2007/0045780 (2007-03-01), Akram et al.
patent: 1601752 (2005-03-01), None
patent: 0 363 256 (1990-04-01), None
patent: 1 408 547 (2004-04-01), None
patent: 1408547 (2004-04-01), None
Masahiro Sekiguchi, Hideo Numata, Ninao Sato, Tatsuhiko Shirakawa, Mie Matsuo, Hiroshi Yoshikawa, Mitsuhiko Yanagida, Hideo Nakayoshi, Kenji Takahashi; Novel low cost integration of through chip interconnection and application to cmos image sensor; IEEE: Electronic Components and Technology Conference (ECTC), Jul. 5, 2006; p. 1367-1374.
Masahiro Sekiguchi et al.; Novel low cost integration of through chip interconnection and application to cmos image sensor; 2006 Electronic Components and Technology Conference; Jul. 5, 2006; p. 1367-1374.
International Search Report and Written Opinion, Feb. 6, 2009.
Leib and Seidemann, “Opto-WLP Technology,”Advanced Packaging, pp. 28, 30, May/Jun. 2006.
Ostmann et al., “Stackable Packages with Integrated Components,”2003 Electronics Packaging Technology Conference, pp. 19-23, Jun. 2003.
Sekiguchi et al., “Novel Low Cost Integration of Through Chip Interconnection and Application to CMOS Image Sensor,”2006 Electronic Components and Technology Conference, pp. 1367-1374, Jun. 2006.
Wu and Poo, “Fabrication of Tapered Through-Vias on (100) Silicon for Wafer Level Packaging,” undated.

Affiliated with

Also associated with

Rating

Packaging methods for imager devices does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Packaging methods for imager devices, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Packaging methods for imager devices will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2724144