Packaging method of a plurality of chips stacked on each...

Details Packaging method of a plurality of chips stacked on each... Packaging method of a plurality of chips stacked on each...

2006-07-25

2008-10-14

Zarneke, David A (Department: 2891)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

Multiple housings

C257S660000, C257SE23114, C257SE23115, C257SE25011, C257SE25013

Reexamination Certificate

active

07436055

ABSTRACT:
A package structure with a plurality of chips stacked on each other includes a substrate, a first chip and second chip. The substrate has a dielectric layer, a metal layer having a conducting trace area and a shielding area formed on the dielectric layer, and a solder mask formed on the conducting trace area. The first chip and the second chip are electrically connected to the conducting trace area and arranged on the solder mask respectively. The first chip has a package body connected with one surface of the metal layer for arranging the first chip between the solder mask and the shielding area of the metal layer. The second chip has a package body connected with the other surface of the metal layer for arranging the second chip between the solder mask and the shielding area of the metal layer.

REFERENCES:
patent: 6534391 (2003-03-01), Huemoeller et al.
patent: 7033911 (2006-04-01), Manepalli et al.
patent: 2001/0008306 (2001-07-01), Kamei et al.

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