Packaging for multi-processor shared-memory system

Details Packaging for multi-processor shared-memory system Packaging for multi-processor shared-memory system

2003-01-08

2004-09-21

Stoner, Kiley (Department: 1725)

Metal fusion bonding

Process

Plural joints

C228S175000, C228S180220

Reexamination Certificate

active

06793123

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to packaging for a multi-processor shared-memory system.
2. Related Art
Multiple chip packages have electrically conductive interconnections therein. Such interconnections, including solder balls, solder columns, etc., are subject to failure due to thermally induced stresses on the interconnections. Thus, there is a need for a multiple chip package having reduced thermally induced stresses on electrically conductive interconnections therein.
SUMMARY OF THE INVENTION
The present invention provides an electrical structure, comprising:
a circuitized substrate comprising a dielectric material and at least one metal layer;
a first stiffener coupled to a first surface of the substrate, wherein the first stiffener includes a first stiffener material;
a second stiffener coupled to a second surface of the substrate, wherein the second stiffener includes a second stiffener material;
a semiconductor memory chip; and
N semiconductor logic chips such that N is at least 2,
wherein each logic chip is electrically coupled to the memory chip by a direct interconnect path that includes a corresponding conductive member,
wherein the corresponding conductive member is in electrical and mechanical contact with both an electrically conductive pad on a surface of the corresponding logic chip and a corresponding electrically conductive pad on a surface of the memory chip,
wherein at least one chip selected from the group consisting of the memory chip, a first logic chip of the N logic chips, a second logic chip of the N logic chips, . . . , a N
th
logic chip of the N logic chips, and combinations thereof, is electrically coupled to the substrate by corresponding solder interconnects, and
wherein each solder interconnect of the corresponding solder interconnects is in electrical and mechanical contact with both an electrically conductive pad on a surface of the substrate and an electrically conductive pad on a surface of the corresponding chip of the at least one chip.
The present invention provides an electrical structure, comprising:
a circuitized substrate comprising dielectric material and at least one metal layer;
a first stiffener coupled to a first surface of the substrate, wherein the first stiffener includes a first stiffener material;
a second stiffener coupled to a second surface of the substrate, wherein the second stiffener includes a second stiffener material;
a semiconductor memory chip; and
N semiconductor logic chips such that N is at least 2,
wherein each logic chip is electrically coupled to the memory chip by a corresponding logic-to-memory path that includes a first conductive member, an electrically conductive via path through the substrate, and a second conductive member,
wherein the first conductive member and a second conductive member are respectively coupled electrically to opposite ends of the electrically conductive via path,
wherein the first conductive member is in electrical and mechanical contact with an electrically conductive pad on a surface of the corresponding logic chip,
wherein the second conductive member is in electrical and mechanical contact with an electrically conductive pad on a surface of the memory chip, and
wherein each logic chip is electrically coupled to the substrate by at least one of the first conductive member and a third conductive member.
The present invention provides a multiple chip package having reduced thermally induced stresses on electrically conductive interconnections therein.


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