Packaging electrical circuits

Details Packaging electrical circuits Packaging electrical circuits

1998-06-03

2000-08-01

Tolin, Gerald

Electricity: conductors and insulators

Conduits, cables or conductors

Preformed panel circuit arrangement

174 35R, 361816, H05K 334

Patent

active

060969814

ABSTRACT:
A structure including a thermally conductive baseplate, an electrical insulator attached to the baseplate, and a metallic shield mounted on the insulator is set forth. The structure also includes an integrated power device having a power-dissipating electronic device, and a first metal layer connected to the shield through a solder joint. A substrate includes an aperture, and the integrated power device is mounted with the power-dissipating device sitting within the aperture. The substrate also includes a conductive run electrically connected to a second metal layer of the integrated power device. A further structure including an electrical conductor and a sheet of conductive material including a punt soldered to the electrical conductor is presented.

REFERENCES:
patent: 3071854 (1963-01-01), Pighini
patent: 3429040 (1969-02-01), Miller
patent: 3621338 (1971-11-01), Rogers et al.
patent: 3683241 (1972-08-01), Duncan
patent: 3737729 (1973-06-01), Carney
patent: 4218724 (1980-08-01), Kaufman
patent: 4278990 (1981-07-01), Fichot
patent: 4315175 (1982-02-01), Hamilton
patent: 4400762 (1983-08-01), Bartley et al.
patent: 4417296 (1983-11-01), Schelhorn
patent: 4531145 (1985-07-01), Wiech, Jr.
patent: 4551746 (1985-11-01), Gilbert et al.
patent: 4551747 (1985-11-01), Gilbert et al.
patent: 4649461 (1987-03-01), Matsuta
patent: 4650107 (1987-03-01), Keser
patent: 4724283 (1988-02-01), Shimada et al.
patent: 4740414 (1988-04-01), Shaheen
patent: 4750089 (1988-06-01), Derryberry et al.
patent: 4769525 (1988-09-01), Leatham
patent: 4783695 (1988-11-01), Eichelberger et al.
patent: 4783697 (1988-11-01), Benenati et al.
patent: 4793543 (1988-12-01), Gainey et al.
patent: 4823235 (1989-04-01), Suzuki
patent: 4847136 (1989-07-01), Lo
patent: 4872081 (1989-10-01), Murphy et al.
patent: 4879630 (1989-11-01), Boucard et al.
patent: 4918811 (1990-04-01), Eichelberger et al.
patent: 4953005 (1990-08-01), Carlson et al.
patent: 4985097 (1991-01-01), Matsumura et al.
patent: 4990490 (1991-02-01), Pathare
patent: 4994215 (1991-02-01), Wiech, Jr.
patent: 4996116 (1991-02-01), Webster et al.
patent: 5006673 (1991-04-01), Freyman et al.
patent: 5019941 (1991-05-01), Craft
patent: 5019946 (1991-05-01), Eichelberger et al.
patent: 5028987 (1991-07-01), Neugebauer et al.
patent: 5176309 (1993-01-01), Horiguchi et al.
patent: 5216279 (1993-06-01), Nakao
patent: 5271548 (1993-12-01), Maiwald
patent: 5280850 (1994-01-01), Horiguchi et al.
patent: 5296735 (1994-03-01), Fukunaga
patent: 5324890 (1994-06-01), Lawlyes
patent: 5328751 (1994-07-01), Komorita et al.
patent: 5365403 (1994-11-01), Vinciarelli et al.
patent: 5372295 (1994-12-01), Abe et al.
patent: 5447267 (1995-09-01), Sakai et al.
patent: 5906310 (1999-05-01), Vinciarelli
patent: 5911356 (1999-06-01), Tsurusaki
Gates and Yokoro, "Sealed Chip-On Board Circuit Protection:", 3.sup.rd International SAMPE Electronics Conference, Jun. 20-22, 1989, pp. 929-938.

Affiliated with

Also associated with

Rating

Packaging electrical circuits does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Packaging electrical circuits, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Packaging electrical circuits will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-665890