Packaging assembly and method of assembling the same

Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor

Reexamination Certificate

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Details

C438S108000, C438S612000, C257S778000, C257S779000, C257S780000

Reexamination Certificate

active

10902055

ABSTRACT:
A packaging assembly includes a substrate; chip-site lands disposed on the first surface; first solder balls connected to the chip-site lands; second solder balls connected to the first solder balls including solder materials having higher melting temperatures than the first solder balls; a semiconductor chip having a plurality of bonding pads connected to the second solder balls on a surface of the semiconductor chip; and an underfill resin disposed around the first and second solder balls.

REFERENCES:
patent: 2002/0149117 (2002-10-01), Shibata
patent: 2004/0155358 (2004-08-01), Iijima
patent: 8-064717 (1996-03-01), None
patent: 10-294337 (1998-11-01), None
patent: 10-321755 (1998-12-01), None
patent: 2000-082716 (2000-03-01), None
patent: 2001-298051 (2001-10-01), None
patent: 2002-016211 (2002-01-01), None
patent: 2002-241469 (2002-08-01), None
patent: WO 02/44241 (2002-06-01), None
Notice of Grounds for Rejection issued by the Japanese Patent Office on Aug. 17, 2005, for Japanese Application No. 2003-170905, and English-language translation thereof.

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