Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Reexamination Certificate
2007-05-08
2007-05-08
Whitehead, Jr., Carl (Department: 2813)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
C438S108000, C438S612000, C257S778000, C257S779000, C257S780000
Reexamination Certificate
active
10902055
ABSTRACT:
A packaging assembly includes a substrate; chip-site lands disposed on the first surface; first solder balls connected to the chip-site lands; second solder balls connected to the first solder balls including solder materials having higher melting temperatures than the first solder balls; a semiconductor chip having a plurality of bonding pads connected to the second solder balls on a surface of the semiconductor chip; and an underfill resin disposed around the first and second solder balls.
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Notice of Grounds for Rejection issued by the Japanese Patent Office on Aug. 17, 2005, for Japanese Application No. 2003-170905, and English-language translation thereof.
Homma Soichi
Tomono Akira
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Jr. Carl Whitehead
Rodgers Colleen E.
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