Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Including contaminant removal or mitigation
Reexamination Certificate
2000-07-27
2004-03-23
Graybill, David E. (Department: 2827)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Including contaminant removal or mitigation
C438S117000, C438S118000, C438S119000, C438S122000, C438S124000, C438S126000, C438S127000
Reexamination Certificate
active
06709895
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the art of electronic packaging and more specifically relates to assemblies incorporating microelectronic devices such as semiconductor chips, methods of making such assemblies, and components for making the same.
Modern electronic devices utilize semiconductor integrated circuits or “chips” which incorporate numerous electronic components. These chips are mounted on substrates which physically support the chips and electrically interconnect each chip with other elements of the circuit. The substrate may be a part of a discrete chip package used to hold a single chip. Alternatively, in a so-called “hybrid circuit” or “module”, one or more chips are mounted to a substrate forming a circuit panel arranged to interconnect the chips and the other circuit elements mounted on the substrate. In each case, the chip must be securely held on the substrate and must be provided with reliable electrical interconnection to the substrate. The electrical interconnections may include numerous input/output or “I/O” connections for carrying signals and/or power to the chip.
The structures utilized to provide the “first level” interconnection between a chip and the substrate should accommodate all of the electrical interconnections in a relatively compact region of the substrate. Moreover, the first level interconnection structures ordinarily are subject to strain caused by thermal cycling as temperatures in the assembly change. The electrical power dissipated within the chip tends to heat the chip and the substrate, so that temperatures of the chip and substrate rise and fall as the device is turned on and off. Differential thermal expansion of the chip and substrate cause the contacts on the chip to move relative to the connected electrical contact pads on the substrate during each heating and cooling cycle of the chip (“thermal cycling”). This tends to cause fatigue of the elements connecting individual contacts and contact pads.
The chip package should be capable of dissipating the heat generated by operation so as to limit the temperature rise of the chip. Additionally, the chip package should provide physical protection to the chip and to the electrical connections between the chip and substrate. Thus, the package should protect the chip and the electrical interconnections from corrosion or other chemical damage. The cost of the chip and the substrate assemblies is also a concern. All of these factors, taken together, present a considerable engineering challenge.
One common approach to the chip mounting problem is referred to as a “die attach/wire bond package.” The die attach/wire bond package, along with other alternatives, is generally described in Multichip Module-Technologies and Alternatives—The Basics: Doane and Franzon, eds. pp. 56-69. In the die attach/wire bond process, also referred to as a “face up” wire bond package or simply as a “wire bond” package the chip is placed on a substrate with the contact-bearing front face of the chip facing upwardly, away from the substrate. The rear face of the chip is bonded to the substrate by a material commonly referred to as a die bond material. Fine gold or aluminum wires are connected between individual contacts on the chip and individual contact pads on the substrate. The entire assembly may be contained in an outer package which is filled with an encapsulant or “potting” compound such as a relatively soft silicone or other elastomer. Because the rear face of the chip is connected to the substrate by the die bond adhesive, the wire bond package provides reasonable thermal dissipation from the chip to the substrate. The individual chips must be handled in a “bare” or unpackaged condition during assembly to the substrate. This special handling, and the wire bonding process itself, require considerable care and special operations. However, typical die attach materials having very high thermal conductivity, such as silver or ceramic filled epoxies, are relatively stiff and noncompliant. When a continuous layer of such a material is applied between the chip and the substrate, it can fail during thermal cycling. Further, voids can occur in a layer of die attach material. Gases trapped in voids can cause failure of the package during service. Moreover, it is difficult to test any individual chip at full operating speed before the chip is mounted to the substrate.
As described in PCT International Publication WO 92/05582 and in U.S. Pat. No. 5,347,159, the disclosures of which are incorporated by reference herein, a semiconductor chip assembly may be provided with a flexible, sheet-like backing element overlying the rear face of the chip. Terminals on the backing element are connected to contacts on the front face of the chip, as by leads extending alongside the edges of the chip. A compliant layer may be provided between the terminals on the backing element and the chip itself, so that the terminals remain movable with respect to the chip. A cover may overlie the front of the chip and may be filled with an encapsulant. The entire assembly may be handled and mounted using essentially the same techniques as are used for surface mounting of conventional components on printed circuit boards. Thus, the terminals of the package can be bonded to contact pads on the substrate using masses of solder disposed between the terminals and contact pads. Prior to mounting, the chip assembly can be tested by engaging a test fixture with the terminals. Such a package typically provides relatively good thermal conductivity between the chip and the package so that the package can serve as a heat sink. However, such a package typically provides limited thermal conductivity between the chip and the substrate.
A chip package sold under the designation Micro-Star BGA by Sharp Corporation and by Texas Instruments, Inc. also includes a chip in a face-up disposition. A flexible polyimide film overlies the back surface of the chip. Wire bonds connect terminals on the front face of the chip to trace terminals on the flexible polyimide film. These terminals in turn can be bonded to a chip by solder balls. A die attach adhesive and a solder mask layer are interposed between the rear face of the chip and polyimide layer. The wire bonds and the chip are covered by a molded epoxy cover. Voids and delaminations in the die attach layer can cause rupture of such a package during thermal cycling. Moreover, such packages typically provide relatively low thermal conductivity from the chip to the substrate.
Additionally, encapsulated metallic conductors such as wire bonds are susceptible to fatigue failures. Typical wire bonds incorporate sharp corners and sharp changes in cross-sectional area at junctions between the fine bonding wire and the connected parts. For example, in a “ball-bond,” each fine wire joins a relatively massive ball of wire material at one end. These features tend to create stress concentrations at the junctures. If the wire is flexed repeatedly during service, it can fail at such stress concentrations. Where the wire is encapsulated in a rigid material, differential thermal expansion of the chip and encapsulant can cause repeated flexure of the wire and fatigue failure. Attempts have been made to avoid such fatigue failures by using very soft encapsulants such as soft elastomers or gel. However, these attempts have not been entirely successful; fatigue failure of encapsulated wire bonds remains a significant problem, even with relatively soft encapsulants.
Accordingly, further improvements in microelectronic packaging would be desirable.
SUMMARY OF THE INVENTION
The present invention provides such further improvements. One aspect of the present invention provides a semiconductor chip assembly which includes a dielectric element, having top and bottom surfaces such as a flexible, sheetlike element. A semiconductor chip is mounted above the top surface of the dielectric element with the rear surface of the chip facing downwardly towards the dielectric element and with the front surface, bearing contacts, facin
Graybill David E.
Lerner David Littenberg Krumholz & Mentlik LLP
Tessera Inc.
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