Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Reexamination Certificate
2011-01-04
2011-01-04
Geyer, Scott B (Department: 2812)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
C257S678000
Reexamination Certificate
active
07863090
ABSTRACT:
Circuit structures and methods of fabrication are provided for facilitating implementing a complete electronic system in a compact package. The circuit structure includes, in one embodiment, a chips-first multichip base layer with conductive structures extending therethrough. An interconnect layer is disposed over the front surface of the multichip layer and includes interconnect metallization electrically connected to contact pads of the chips and to conductive structures extending through the structural material. A redistribution layer, disposed over the back surface of the multichip layer, includes a redistribution metallization also electrically connected to conductive structures extending through the structural material. Input/output contacts are arrayed over the redistribution layer, including over the lower surfaces of at least some integrated circuit chips within the multichip layer, and are electrically connected through the redistribution metallization, conductive structures, and interconnect metallization to contact pads of the integrated circuit chips of the multichip layer.
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Eichelberger Charles W.
Kohl James E.
EPIC Technologies, Inc.
Geyer Scott B
Heslin Rothenberg Farley & & Mesiti P.C.
Radigan, Esq. Kevin P.
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