Package structure with increased capacitance and method

Details Package structure with increased capacitance and method Package structure with increased capacitance and method

2005-08-30

2005-08-30

Clark, Jasmine (Department: 2815)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

C438S379000, C438S381000, C438S396000

Reexamination Certificate

active

06936498

ABSTRACT:
A package with increased capacitance comprises a core and a plurality of buildup layers. The core has an inner dielectric portion and the core outer conductive layer. The buildup layers are disposed over the core and have offset ablated regions reducing the thickness of the buildup layers in the ablated regions. Conductive material is plated on the buildup layers including within the ablated regions. The reduced thickness and increased plate area due to the ablated regions increases the capacitance between adjacent buildup layers. Processors and processing systems may take advantage of the increased capacitance in the package to draw more current and operate at higher data rates.

REFERENCES:
patent: 5177670 (1993-01-01), Shinohara et al.
patent: 5625221 (1997-04-01), Kim et al.
patent: 2003/0096447 (2003-05-01), Lao et al.
patent: 2003/0173673 (2003-09-01), Val
patent: 2003/0222314 (2003-12-01), Nair
patent: 2004/0002187 (2004-01-01), Block et al.

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