Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Multiple housings
Reexamination Certificate
2000-12-22
2002-07-02
Ho, Hoai V. (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Multiple housings
C257S686000, C257S777000
Reexamination Certificate
active
06414384
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a package structure stacking chips on a front surface and a back surface of a substrate. More specifically, the present invention relates to a structure of ball grid array package stacking chips on a front surface and a back surface of a substrate.
2. Description of the Related Art
Recently, an integrated circuit plays an important role in our daily life. Many products obtained from integrated circuit devices are always used. With increasing development in electronics, electronic products having humanized operation and higher performance are available. However, various products are designed such that the features, such as lesser weight and compact size, are provided for comfortable use. In the semiconductor fabricating process, a semiconductor product having higher integration is available because of mass production of the 0.18 micrometer integrated circuit.
In general, the production of an integrated circuit (IC) includes three stages: silicon wafer production, semiconductor process and IC packaging.
Various technologies for IC packaging have been developed due to competition in the market. Many high-density packages such as chip scale package (CSP), wafer level package or multiple chip module (MCM) are manufactured. In device assembly, a multi-level PCB having higher density can be used to allow the IC packaging to be arranged on the PCB more compactly.
The current IC packaging for the integrated circuit has been developed to incorporated a Read Only Memory (ROM), a Static Random Access Memory (SRAM), a flash memory or a Dynamic Random Access Memory (DRAM), a Logic Circuit, and a digital circuit into a chip, known as System On Chip (SOC) to satisfy the demand for light weight, compact size and perfect performance. An embedded ROM is one embodiment of the circuit having both a flash memory and a logic circuit.
However, in the conventional system on chip (SOC), a plurality of chips, such as DRAM, flash memory, Logic Circuit and radio frequency (RF) devices, are incorporated into a chip. Although the functionality and electric property thereof can be thus enhanced, it is more complicated to design a layout in circuit connection. Since the fabrication methods for devices having various functions are different from each other, the fabrication for devices having various functions becomes complex, resulting in reduced yield and increased cost of fabrication.
One way to solve the above captioned problems is to adopt stacked chips that are usually used in a ball grid array package, for example, to increase the capacity of memory.
Referring to
FIG. 1
, a cross sectional view of a conventional package structure is shown.
As shown in
FIG. 1
, a first chip
106
is deposited on a substrate
102
, and a second chip
108
is stacked on the first chip
106
. The first chip
106
and the second chip
108
are adhered by a glue layer
104
. Wire bonding is then performed to electrically connect the first chip
106
and the second chip
108
to the substrate
102
by wires
110
a
and
110
b,
respectively. The substrate
102
, the first chip
106
, the second chip
108
and the wires
110
a
and
110
b
are then encapsulated with a mold compound
114
. Finally, solder balls
112
are mounted on the substrate
102
to complete a ball grid array package (BAG).
However, the first chip must be much larger than the second chip in BGA, with difference of the lengths of the first chip and the second chip being at least 0.3 mm. If the difference is smaller than 0.3 mm, wire bonding cannot be performed or the second chip contacts the wire
110
a.
Referring to
FIG. 2
, a cross sectional view of a conventional flip chip package is shown.
As shown in
FIG. 2
, U.S. Pat. No. 5,801,072 discloses a substrate
202
having a front surface
201
and a back surface
203
opposite to the front surface
201
. A first chip
206
is deposited on the front surface
201
of the substrate
202
, and a second chip
208
is correspondingly deposited on the back surface
203
of the substrate
202
. The first chip
206
and the second chip
208
are provided on the substrate
202
by flip chip technology and have substantially the same size. The first chip
206
is encapsulated with a mold compound
214
. Finally, solder balls
212
are mounted on the back surface
203
of the substrate
202
to complete a package.
In such package, only the first chip
206
is provided on only the front surface
201
of the substrate
202
by flip chip technology and relatively limited performance for the integration of the chips.
Referring to
FIGS. 3A and 3B
, a top view and cross sectional view of another conventional multiple chip module are shown.
FIG. 3B
is a cross sectional view of
FIG. 3A
along
3
B—
3
B.
As shown in
FIGS. 3A and 3B
, a multiple chip module (MCM) package is disclosed. A main chip
305
, a first chip
306
and a second chip
308
are arranged side-by-side on a substrate
302
. The connection of the main chip
305
, the first chip
306
and the second chip
308
to the substrate
302
is achieved by a glue layer
304
. Wire bonding is subsequently performed to electrically connect the main chip
305
, the first chip
306
and the second chip
308
to the substrate
302
by wires
310
. The substrate
302
, the main chip
305
, the first chip
306
, the second chip
308
and the wires
310
are encapsulated with a mold compound
314
. Finally, solder balls
312
are mounted on the substrate
302
to complete a multiple chip module package.
The main characteristic for a conventional multiple chip module package structure is to integrate devices having multiple functions into a package. Because the area occupied by the devices is large so as to make routability of the substrate
302
complicated, a substrate
302
having high trace density is thus desirably used. The side-by-side arrangement of the main chip
305
, the first chip
306
and the second chip
308
influences adversely the amount of chips that can be accommodated in the multiple chip module package, therefore resulting in lowered integration, increased production cost and reduced performance.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a package structure stacking chips having substantially the same size on the front surface and the back surface of the substrate.
It is another object of the present invention to provide a package structure which integrates chips having substantially the same size in various directions on the front surface and the back surface of the substrate.
It is another object of the present invention to provide a package structure integrating chips having substantially the same size in various directions, in which the front surface of the substrate is subject to wire bonding and the back surface thereof is subject to a flip chip process.
It is still another object of the present invention to provide a package structure integrating chips having substantially the same size in various directions, in which multiple chips are stacked on the front and back surfaces without changing the dimensions of the original package.
According to the above objects of the present invention, a package structure stacking multiple chips on a front surface and a back surface of a substrate comprises at least a substrate, a plurality of chip sets, a plurality of support members, a plurality of glue layers, a plurality of wires, a plurality of flip chips and a mold compound. The substrate has a front surface and a back surface opposite to the front surface. A plurality of chip sets comprises one or more chips having a plurality of bonding pads, while stacking on the front surface of the substrate as a laminate. A plurality of support members are arranged between each two adjacent chip sets. The connections between the support members, the chip sets, and the substrate are achieved by a plurality of glue layers. Chip sets are electrically connected to each other or to the substrate. Finally, the front surface of the substrat
Huang Chien-Ping
Lo Randy H. Y.
Wu Chi-Chuan
Ho Hoai V.
J. C. Patents
Nguyen Thinh T
Silicon Precision Industries Co., Ltd.
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