Package structure and manufacturing method thereof

Details Package structure and manufacturing method thereof Package structure and manufacturing method thereof

2011-08-02

2011-08-02

Pizarro, Marcos D. (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

With window means

C257S678000, C257S730000, C257S788000, C257SE23001

Reexamination Certificate

active

07989937

ABSTRACT:
A package structure and a manufacturing method thereof are provided. The package structure includes a substrate, a chip and a packing material layer. The substrate has a top surface and a lateral surface. The top surface is connected with the lateral surface. The chip is disposed on the top surface. The packing material layer comprises a body portion and an extending portion. The body portion covers at least a part of the chip and the substrate. The extending portion is connected with the body portion and covers at least a part of the substrate. The extending portion is projected to the lateral surface and made from a transparent material.

REFERENCES:
patent: 5355016 (1994-10-01), Swirbel et al.
patent: 2005/0205980 (2005-09-01), Manansala
patent: 451339 (2001-08-01), None
Watlow Elelctric Manufacturing Company “Kapton Material”, 2001.

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