Package structure and fabrication method thereof

Active solid-state devices (e.g. – transistors – solid-state diode – Encapsulated

Reexamination Certificate

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Details

C257S794000, C257SE23116, C257SE23127

Reexamination Certificate

active

07638887

ABSTRACT:
A package structure and fabrication method thereof. The structure includes a substrate having a terminal, a chip overlying the substrate, the chip having an active surface, having a center region and periphery region, the periphery region having an electrode thereon, a patterned cover plate overlying the chip and exposing the electrode, a conductive material electrically connecting the electrode and terminal, and an encapsulant covering the terminal, conductive material, and electrode, but exposing the cover plate overlying the center region of the chip.

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patent: 6900531 (2005-05-01), Foong et al.
patent: 7183589 (2007-02-01), Kameyama et al.
patent: 2001/0034083 (2001-10-01), Coyle et al.
patent: 2004/0080037 (2004-04-01), Foong et al.
patent: 2007/0096312 (2007-05-01), Humpston et al.
patent: 05-074867 (1993-03-01), None
patent: 2000-323614 (2000-11-01), None
patent: 2000-349202 (2000-12-01), None
patent: 2004-319530 (2004-11-01), None
patent: 094116089 (1993-07-01), None

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