Package of integrated circuits and vertical integration

Details Package of integrated circuits and vertical integration Package of integrated circuits and vertical integration

1999-12-06

2001-11-27

Bowers, Charles (Department: 2813)

Stock material or miscellaneous articles

All metal or with adjacent metals

Composite; i.e., plural, adjacent, spatially distinct metal...

C438S108000, C438S459000, C438S977000

Reexamination Certificate

active

06322903

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to semiconductor circuits, and more particularly to integrated circuit packaging and to vertical integrated circuits.
Integrated circuits are typically attached to a wiring substrate, for example, a printed circuit board (PCB), for easy connection to other circuits. Attachment can be done using flip-chip technology. According to this technology, conductive bumps are formed on the contact pads of the chip (die) incorporating the circuit. The bumps can be made by growing solder on the contact pads or by electroplating gold or some other material. Then the chip is bonded with its bumps to the wiring substrate.
Sometimes, the contacts on the wiring substrate cannot be made with the same precision as the contacts on the chip. For example, typical PCB fabrication technology is not as precise as semiconductor fabrication technology used for chip fabrication. Therefore, the chip contacts have to be made larger, and spaced farther from each other, to accommodate PCB fabrication technology.
Another reason why the chip contacts cannot be made as dense as allowed by the semiconductor fabrication technology is large tolerances required by many bumping processes.
This problem is exacerbated by the fact that the chip contacts placement is sometimes restricted by the layout of the chip circuitry. For example, many chips have their contacts restricted to the peripheral area. This makes it more difficult to accommodate larger widely spaced contacts as required by the PCB technology and bumping processes.
Therefore, sometimes a chip is bonded to a molded plastic substrate, which is bonded to the PCB. The plastic substrate can be larger than the chip, or it can have the same size. On the plastic substrate, the position of the contacts bonded to the PCB is not as limited as on the chip. For example, the contacts can be evenly distributed on the plastic substrate's surface bonded to the PCB (so-called “area matched package”).
Alternative packaging techniques are desirable.
SUMMARY
In some embodiments of the present invention, the intermediate substrate between a chip and a wiring substrate is made using techniques common in semiconductor fabrication technology. In particular, the substrate can be made from a semiconductor material (for example, silicon) or insulating polymer. The substrate has contacts both on the side connected to the chip and on the side connected to the PCB. These contacts are made using techniques similar to those used for vertical integration. See, for example, PCT publication WO 98/19337 “Integrated Circuits and Methods for Their Fabrication” (TruSi Technologies, LLC, 1998).
In some embodiments, the intermediate substrate (the “packaging” substrate) includes additional circuitry.
In some embodiments, a fabrication method comprises forming one or more vias in a first side of a first substrate. A conductive contact is formed in each of the vias so that each contact is not exposed on a second side of the first substrate. Then a blanket process exposes each contact on the second side. The blanket process includes removing material from the second side. The blanket process causes each contact to protrude from the second side. At least one contact on the second side is bonded to a wiring substrate so that the first substrate or a portion thereof becomes directly attached to the wiring substrate.
According to another aspect of the invention, a method for fabricating a vertical integrated circuit comprises providing a vertically integrated stack of structures M(
1
), . . . M(N), wherein each structure comprises one or more contacts directly attached to one or more contacts of another one of said structures. The structure M(N) is an end structure in the stack, and the structure M(N) comprises a first side not attached to any other one of said structures. The first side of the structure M(N) is processed with a blanket process comprising blanket removal of material from the first side. The blanket process exposes one or more first contacts protruding from the first side by at least a predetermined amount.
According to another aspect of the invention, a fabrication method comprises providing a structure S
1
comprising a semiconductor substrate with circuitry adjacent to a first side of the structure. Material is removed from a second side of the structure S
1
to expose one or more first contact structures, wherein the material is removed at least until the one or more first contact structures protrude from the second side by at least a predetermined amount, and wherein the material removal is a blanket removal process. Flowable material is deposited on the second side, wherein the flowable material is dielectric when hardened. The flowable material is subjected to a blanket material-removal process at least until the one or more first contact structures protrude on the second side by at least a predetermined amount, so that after the removal process the hardened flowable material covers the substrate on the second side.
In some embodiments, each first contact structure comprises a conductive contact and a dielectric covering the conductive contact on the second side. The removal process is followed by removing the dielectric to expose the conductive contact in each first contact structure. After the dielectric removal the hardened flowable material still covers the substrate on the second side.
According to another aspect of the invention, one or more vias are made in a first side of a first semiconductor wafer along one or more scribe lines. The first side of the first wafer is bonded to a second wafer. Material is removed from a second side of the first wafer until the vias become through holes. In some embodiments, the one or more vias form a groove completely surrounding at least one die in the first wafer.
According to another aspect of the invention, a structure comprises a first semiconductor wafer bonded to a second semiconductor wafer. The first wafer has one or more through holes on a boundary of at least one die of the first wafer.
According to another aspect of the invention, a first chip or wafer comprises a substrate made of a semiconductor or insulating material. The substrate comprises one or more through holes therein and a first contact in each of the through holes. Each contact comprises at least one conductive layer protruding from the first chip or wafer through at least one hole and also extending inside the substrate laterally away from the hole. The contacts are directly attached to a wiring substrate. The wiring substrate is a non-semiconductor substrate, or the wiring substrate is a semiconductor substrate without any active devices. The wiring substrate has one or more conductive lines for providing electrical connection to the first chip.
Some other features and advantages of the invention are described below. The invention is defined by the appended claims.


REFERENCES:
patent: 3810129 (1974-05-01), Behman et al.
patent: 3811117 (1974-05-01), Anderson, Jr. et al.
patent: 3881884 (1975-05-01), Cook et al.
patent: 3993917 (1976-11-01), Kalter
patent: 4368106 (1983-01-01), Anthony
patent: 4394712 (1983-07-01), Anthony
patent: 4463336 (1984-07-01), Black et al.
patent: 4467518 (1984-08-01), Bansal et al.
patent: 4603341 (1986-07-01), Bertin et al.
patent: 4612083 (1986-09-01), Yasumoto et al.
patent: 4628174 (1986-12-01), Anthony
patent: 4722130 (1988-02-01), Kimura et al.
patent: 4769738 (1988-09-01), Nakamura et al.
patent: 4807021 (1989-02-01), Okumura
patent: 4842699 (1989-06-01), Hua et al.
patent: 4890784 (1990-01-01), Bampton
patent: 4897708 (1990-01-01), Clements
patent: 4954458 (1990-09-01), Reid
patent: 4978639 (1990-12-01), Hua et al.
patent: 4996587 (1991-02-01), Hinrichsmeyer et al.
patent: 5064771 (1991-11-01), Solomon
patent: 5071792 (1991-12-01), VanVonno et al.
patent: 5160987 (1992-11-01), Pricer et al.
patent: 5166097 (1992-11-01), Tanielian
patent: 5191405 (1993-03-01), Tomita et al.
patent: 5225771 (1993-07-01), Leedy
patent: 5258330 (1993-11-01), Khandros et al.
patent: 5270

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