Package level ESD protection and method therefor

Details Package level ESD protection and method therefor Package level ESD protection and method therefor

2008-05-15

2011-11-15

Fureman, Jared (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

High voltage dissipation

C361S056000, C361S091100, C361S111000

Reexamination Certificate

active

08059380

ABSTRACT:
A semiconductor package includes an electrostatic discharge rail capable of being coupled to a first conductive contact and a second conductive contact, a first portion of a voltage triggerable material between the electrostatic discharge rail and the first conductive contact; and a second portion of the voltage triggerable material between the electrostatic discharge rail and the second conductive contact. The first and second conductive contacts may be coupled to the same semiconductor device or different semiconductor devices.

REFERENCES:
patent: 5869869 (1999-02-01), Hively
patent: 5955762 (1999-09-01), Hively
patent: 6351011 (2002-02-01), Whitney et al.
patent: 7218492 (2007-05-01), Shrier
patent: 7274048 (2007-09-01), Wu
patent: 7285846 (2007-10-01), Tran
patent: 2006/0061925 (2006-03-01), Shrier
patent: 2007/0127175 (2007-06-01), Shrier
patent: 2008/0278873 (2008-11-01), Leduc et al.
patent: 2009/0097175 (2009-04-01), Chiu et al.
Shrier et al; “Embedding a Thin Polymer Voltage ESD Suppressing Core in a Chip Package-Alternative to on Chip ESD Protection”; 16th European Microelectronics and Packaging Conference & Exhibition, Oulu, Finland, Jun. 2007.

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