Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-08-22
2002-11-26
Nguyen, Tuan H. (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C257S693000, C257S698000, C257S700000, C257S777000, C257S778000, C438S106000, C438S125000, C438S612000, C438S614000
Reexamination Certificate
active
06486052
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a package for mounting a semiconductor device (chip) and a solder bump, and its manufacturing method.
2. Description of the Related Art
Generally, when a semiconductor chip and solder bumps are mounted on terminals of a package by soldering or the like, it is impossible to mount the semiconductor chip and the solder bumps directly on the terminals, because the terminals are not made of rust proof material. Therefore, it is essential to electroplate Au or Ni/Au on the terminals before the semiconductor chip and the solder bumps are mounted.
In a prior art method for manufacturing a package for mounting a semiconductor device and a bump, an interposer substrate having a first surface for mounting the semiconductor device is prepared. Then, a conductive layer is formed on a second surface of the interposer substrate, and the conductive layer is patterned to form a wiring layer capable of being connected to the semiconductor device, a terminal connected to the wiring layer, and a plating layer connected to the terminal and terminated at an end of the package. Then, a mask layer having an opening exposing the terminal is coated, and the terminal is electroplated by supplying a current from the plating layer to the terminal (see: JP-A-5-95025 & JP-A-8-288422). This will be explained later in detail.
In the above-described prior art method, however, the plating layer is finally left. Therefore, when the operation frequency of this semiconductor chip is higher, the amount of signals reflected by the plating layer is increased. Also, the parasitic capacitance of the plating layer adversely affects signals from the semiconductor chip to the solder bump and vice versa.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a package and its manufacturing method capable of decreasing the amount of reflected signals and reducing the parasitic capacitance by plating layers.
According to the present invention, in a package for mounting a semiconductor device and a bump, an interposer substrate has a first surface for mounting the semiconductor device. A wiring layer capable of being connected to the semiconductor device, a terminal connected to the wiring layer for mounting the bump, and a plating layer are formed on a second surface of the interposer substrate. The plating layer is connected to one of the terminal and the wiring layer. The plating layer is terminated within the interposer substrate.
Also, in a method for manufacturing a package for mounting a semiconductor device and a bump, an interposer substrate having a first surface for mounting the semiconductor device is prepared. Then, a conductive layer is formed on a second surface of the interposer substrate, and the conductive layer is patterned to form a wiring layer capable of being connected to the semiconductor device, a terminal connected to the wiring layer, and a plating layer connected to the terminal or the wiring layer and terminated at an end of the package. Then, a mask layer having an opening exposing the terminal is coated, and the terminal is electroplated by supplying a current from the plating layer to the terminal. Finally, the plating layer is terminated within the package.
REFERENCES:
patent: 4498122 (1985-02-01), Rainal
patent: 4827327 (1989-05-01), Miyauchi et al.
patent: 5284725 (1994-02-01), Takatsu
patent: 5726489 (1998-03-01), Matsuda et al.
patent: 5851911 (1998-12-01), Farnworth
patent: 6077766 (2000-06-01), Schesta et al.
patent: 6117705 (2000-09-01), Glenn et al.
patent: 6181004 (2001-01-01), Koontz et al.
patent: A 64-50450 (1989-02-01), None
patent: 64-50450 (1989-02-01), None
patent: 5-95025 (1993-04-01), None
patent: 8-288422 (1996-11-01), None
patent: 10173087 (1998-06-01), None
NEC Corporation
Nguyen Tuan H.
Pham Thanhha
Young & Thompson
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