Package having exposed integrated circuit device

Details Package having exposed integrated circuit device Package having exposed integrated circuit device

2009-05-11

2011-11-08

Ha, Nathan (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Physical configuration of semiconductor

With peripheral feature due to separation of smaller...

C257SE21499

Reexamination Certificate

active

08053869

ABSTRACT:
A package (10) includes an integrated circuit device (12) having an electrically active surface (16) and an opposing backside surface (14). A dielectric molding resin (26) at least partially encapsulates the integrated circuit die and the plurality of electrically conductive leads (20) with the backside surface (14) and the plurality of electrical contacts (24) being exposed on opposing sides of the package (10). Features (30) are formed into electrically inactive portions of the integrated circuit die (12) to seal moisture paths and relieve packaging stress. The features (30) are formed by forming a trough (54) partially through the backside (56) of the wafer (40) in alignment with a saw street (48), the trough (54) having a first width; and forming a channel (62) extending from the trough (54) to the electrically active face (42) to thereby singulate the integrated circuit device member, the channel (62) having a second width that is less than the first width.

REFERENCES:
patent: 5872396 (1999-02-01), Kosaki
patent: 5998238 (1999-12-01), Kosaki
patent: 6420776 (2002-07-01), Glenn et al.
patent: 6455920 (2002-09-01), Fukasawa et al.
patent: 6580152 (2003-06-01), Hasegawa
patent: 6607970 (2003-08-01), Wakabayashi
patent: 6642137 (2003-11-01), Yeh et al.
patent: 6657282 (2003-12-01), Fukasawa et al.
patent: 6790709 (2004-09-01), Dias et al.
patent: 6812548 (2004-11-01), Dias et al.
patent: 6815803 (2004-11-01), Reithinger et al.
patent: 6833284 (2004-12-01), Goltl et al.
patent: 6876061 (2005-04-01), Zandman et al.
patent: 6916686 (2005-07-01), Wada et al.
patent: 7691726 (2010-04-01), Seng
patent: 7736944 (2010-06-01), Shizuno
patent: 7763528 (2010-07-01), Kushima et al.
patent: 2001/0035567 (2001-11-01), Fujii
patent: 2002/0185710 (2002-12-01), Zandman et al.
patent: 2003/0020142 (2003-01-01), Wachtler
patent: 2003/0022465 (2003-01-01), Wachtler
patent: 2003/0038343 (2003-02-01), Hasegawa

Affiliated with

Also associated with

Rating

Package having exposed integrated circuit device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Package having exposed integrated circuit device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Package having exposed integrated circuit device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4290754