Package for at least one semiconductor body

Electricity: conductors and insulators – Boxes and housings – Hermetic sealed envelope type

Reexamination Certificate

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Details

C174S050510, C257S788000, C257S793000

Reexamination Certificate

active

06288335

ABSTRACT:

BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to a package for at least one semiconductor body.
A unit of this generic type, which is referred to for short in the following text as a “package component”, may, for example, be a memory module which is intended, for example, for mounting on a printed circuit board configuration.
In the case of complex semiconductor bodies, in particular for memory modules, the number of external contacts, the so-called I/O ports, is increasing. Nowadays, chips with more than a thousand I/O ports exist, and several thousand I/O ports are believed to be possible. In order to match this requirement, the I/O ports in such package components are generally no longer routed out at the chip edge, for space reasons, but the contacts are routed out from one surface of the semiconductor body. Since the connecting pads need not be positioned at the chip edge, the signal can advantageously be routed directly out of the chip at the point where it is produced. These extremely short paths have been found to make such components advantageous—in particular for radio-frequency applications. Furthermore, such a component offers a very small installation area, owing to the relatively small connecting pads.
Such a module may be, for example, a so-called flip chip module. The flip chip module has no package and is in the category of bar dies. The connection technology used here is called C4 and is short for control collapse chip connection. C4 technology has been used for more than 20 years in a large number of products.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a package for at least one semiconductor body which overcome the above-mentioned disadvantages of the prior art devices and methods of this general type, which has a considerably higher chip/package ratio than CSP technology and which can be produced simply and cost-effectively.
With the foregoing and other objects in view there is provided, in accordance with the invention, a package for a semiconductor body, the semiconductor body having a first and a second surface, an edge surface surrounding the semiconductor body, and a plurality of contact points on the first surface, the semiconductor body further having a plurality of connecting elements, at least some of the connecting elements making contact with the contact points and via which the semiconductor body can make electrical contact with a printed circuit board, the package including:
a first part formed of a thin supporting frame for completely surrounding the edge surface of the semiconductor body, the thin supporting frame having an upper rim rising above the second surface of the semiconductor body at the edge surface and the thin supporting frame is formed of a first compound; and
a second part formed of a substantially flat cover for entirely covering the second surface of the semiconductor body and at least partially covering the upper rim of the thin supporting frame, the flat cover is formed of a second compound and the first compound forming the supporting frame has a substantially greater viscosity than the second compound.
Such package components according to the invention are referred to as polymer bumper chip scale packages (PBCSP) in the following text.
The present invention allows all the advantages of flip chip technology and CSP technology to be combined in a simple manner, without having to accept the disadvantages resulting from them.
The major advantage of the present invention is that the PBSCP component according to the invention, which is formed in two parts, has an optimized chip/package ratio owing to the very thin supporting frame. In consequence, the package can be produced simply and very cost-effectively.
Furthermore, the completed package component is protected against external influences and against damage during transport and production. The complete package component can advantageously be laser-marked.
The material for the supporting frame normally has a very high viscosity. Typically, the supporting compound is extremely consistent at room temperature. In contrast, the compound for the cover has a much lower viscosity than the supporting compound. Normally, the supporting compound is applied first and is used, during the next process step, as a flow stop for the cover compound. This prevents the cover compound, which is applied during production and is still liquid, from flowing over the rim of the semiconductor bodies.
A polymer is normally used as the supporting compound. The polymer has a high viscosity at room temperature, and is thus extremely consistent in normal conditions. This is particularly advantageous if the package is transported or handled by machines between the process steps. Other commercially available plastics or similar materials that have a high viscosity at room temperature may also be used as the supporting compound.
A so-called glob top is typically used as the cover compound. The glob top may be, for example, an epoxy resin or some other commercially available resin. It is also feasible for a gel-like substance or something similar to be used as the glob top.
Typically, those regions on the front face of the chip that are not provided with contact points are protected by a passivation layer. In this way, the front face of the chip is protected against environmental influences, such as moisture, humidity, mechanical stress, corrosion etc.
It is particularly advantageous if the regions between the connecting elements and the printed circuit board are filled by a filler. In particular, this protects the contact connections. Connecting element fractures, which lead to a malfunction of the semiconductor component, can be avoided by this measure.
During the production of the package components, it is absolutely essential for those surfaces of the holder which come into contact with the package component to be composed of a non-adhering material. Otherwise, the package components that have just been completed could possibly become damaged when released from the holder.
The non-adhering material should be a material which does not react with the material of the package component at high temperatures. Typically, TEFLON is used as the non-adhering material. However, it is also feasible to use any other material with similar material characteristics.
It is particularly advantageous for the holder for the package components to contain an m×n matrix. This allows a plurality of package components to be processed at the same time, as a result of which the production costs for the package components can be drastically reduced.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a package for at least one semiconductor body, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.


REFERENCES:
patent: 5289346 (1994-02-01), Carey et al.
patent: 5336931 (1994-08-01), Juskey et al.
patent: 5496775 (1996-03-01), Brooks
patent: 5627405 (1997-05-01), Chillara
patent: 5981314 (1999-11-01), Glenn et al.
patent: 6034333 (2000-03-01), Skipor et al.
patent: 19500655A1 (1996-07-01), None
patent: 0 876 030 A2 (1998-11-01), None
patent: 08017864 (1996-01-01), None
patent: 08236586 A (1996-09-01), None
patent: 09107052A (1997-04-01), None
Japanese Patent Abstract No. 02125633 (Kenji), dated May 14, 1990.
Japanese Patent Abstract No. 08335653 (Tadao), dated Dec. 17, 1996.
Japanese Patent Abstract No. 56043748 (Susumu), dated Apr. 22, 1981.
Shinji Baba et al.: “Molded Chip Scale Package for high Pin Count”, 1996 Electronic Components and Technology Conference, pp. 1251-1257.

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