Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Flip chip
Reexamination Certificate
2007-07-03
2007-07-03
Williams, Alexander Oscr (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Flip chip
C257SE23125, C257SE21511, C257S780000, C257S698000, C257S783000, C257S782000, C257S668000, C257S737000, C257S738000, C257S772000, C257S779000, C257S734000, C257S691000
Reexamination Certificate
active
10671334
ABSTRACT:
A buffer layer is formed on a substrate and then electronic devices are packed on the buffer layer in the present invention, and problems of lower hermeticity and complex process in the conventional arts can be avoided. Therefore, the present invention provides a packaging structure and method with a better hermeticity and a simpler process. Especially, due to the buffer layer, the planarization for flip-chip bonding can be improved and reduce negative effects of the packing process.
REFERENCES:
patent: 4545610 (1985-10-01), Lakritz et al.
patent: 4927697 (1990-05-01), Hill
patent: 5120678 (1992-06-01), Moore et al.
patent: 5136366 (1992-08-01), Worp et al.
patent: 5220200 (1993-06-01), Blanton
patent: 5523628 (1996-06-01), Williams et al.
patent: 5557150 (1996-09-01), Variot et al.
patent: 5633535 (1997-05-01), Chao et al.
patent: 5659203 (1997-08-01), Call et al.
patent: 5969461 (1999-10-01), Anderson et al.
patent: 6078229 (2000-06-01), Funada et al.
patent: 6150748 (2000-11-01), Fukiharu
patent: 6214650 (2001-04-01), Nagerl et al.
patent: 6228679 (2001-05-01), Chiu
patent: 6262513 (2001-07-01), Furukawa et al.
patent: 6310421 (2001-10-01), Morishima
patent: 6459164 (2002-10-01), Nagerl et al.
patent: 6492194 (2002-12-01), Bureau et al.
patent: 6560122 (2003-05-01), Weber
patent: 6642626 (2003-11-01), Park
patent: 2001/0040298 (2001-11-01), Baba et al.
patent: 2002/0000895 (2002-01-01), Takahashi et al.
patent: 2002/0149298 (2002-10-01), Furukawa et al.
patent: 2003/0009864 (2003-01-01), Kim et al.
patent: 2003/0047801 (2003-03-01), Azuma
patent: 2003/0090338 (2003-05-01), Muramatsu
patent: 2003/0113054 (2003-06-01), Furuyama
patent: 2003/0127747 (2003-07-01), Kajwara et al.
patent: 2003/0155639 (2003-08-01), Nakamura et al.
patent: 2003/0209813 (2003-11-01), Azuma
patent: 2004/0234689 (2004-11-01), Morganelli et al.
patent: 2005/0056946 (2005-03-01), Gilleo
patent: 2000-299330 (2000-10-01), None
patent: WO 99/43084 (1999-08-01), None
patent: WO 03/012856 (2003-02-01), None
NN87044736, Apr. 1, 1987, Area Array Substrate-To-Carrier Interconnection Corner Standoff, IBM Technical Disclosure Bulletin, Apr. 1987, US; Volumel No. 29, Issue No. 11, Page No. 4736-4737.
NN79081064 IBM Technical Disclosure Bulletin, Aug. 1979, US, “Modulat Cap Monting” vol. # 22; Issue # 3, pp. 1064, Publication date Aug. 1, 1979.
Chih-Hsyong Wu
Yu-Tung Huang
Yung-Cheng Hsu
Perkins Coie LLP
Tai-Saw Technology Co., Ltd.
Williams Alexander Oscr
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