Package and fabricating method thereof

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Wire contact – lead – or bond

Reexamination Certificate

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Details

C257S786000, C257SE23010, C257SE23024, C257SE23037, C257SE23070, C438S121000

Reexamination Certificate

active

07830024

ABSTRACT:
A package and a fabricating method thereof are provided. The package includes a conductive layer, a chip, a plurality of first pads, a plurality of bonding wires and a sealant. The conductive layer has a die pad and includes a plurality of wires. A path of each wire is substantially parallel to a supporting surface of the die pad. Each wire has an upper surface and a lower surface. The chip disposed on the supporting surface has a plurality of pads. The first pads are correspondingly formed on the upper surfaces of the wires. The bonding wires electrically connect the pads of the chip to the first pads. The sealant seals up the conductive layer, the first pads, the chip and the bonding wires, and exposes the lower surface of the conductive layer. The conductive layer projects from a bottom surface of the sealant.

REFERENCES:
patent: 6664138 (2003-12-01), Igarashi et al.
patent: 6720209 (2004-04-01), Igarashi et al.
patent: 6883231 (2005-04-01), Igarashi et al.
patent: 6989291 (2006-01-01), Igarashi et al.
patent: 7030033 (2006-04-01), Igarashi et al.
patent: 7045393 (2006-05-01), Igarashi et al.
patent: 2004/0092129 (2004-05-01), Igarashi et al.
patent: 2004/0097081 (2004-05-01), Igarashi et al.
patent: 2004/0097086 (2004-05-01), Igarashi et al.
patent: 2004/0106288 (2004-06-01), Igarashi et al.

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