Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – Having heterojunction
Reexamination Certificate
2001-07-23
2002-11-05
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
Having heterojunction
C438S413000
Reexamination Certificate
active
06475870
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to the general field of lateral diffused MOS (LDMOS) devices with particular reference to increasing the punch-through voltage.
BACKGROUND OF THE INVENTION
An LDMOS device (Lateral Diffusion Metal Oxide Semiconductor) is basically a MOSFET fabricated using a double diffusion process with coplanar drain and source regions. The present invention is concerned with the particular case of P channel devices. In general, a P-type LDMOS device is difficult to integrate with processes for manufacturing N-type LDMOS devices without adding an extra mask. The main problem is that the P-type LDMOS cannot achieve the same breakdown voltage as its N-type counterpart because of early punch-through.
An N-epitaxial layer is always selected for the formation of LDMOS devices since the N-epi can be used as the drift region of the MOS drain to sustain high voltage. However the drain of a P-type LDMOS is formed by a P-implant process so a P-drain/N-epi/P-substrate structure is formed. When a high negative voltage is applied to the drain of a P-type LDMOS, punch-through to the P-substrate can occur very early.
This is illustrated in
FIG. 1
which shows a typical structure of the prior art. N− body of silicon
12
(that typically has a resistivity between about 0.1 and 1 ohm-cm) is isolated from neighboring devices by P+ boundaries
13
. P− well
18
extends downwards from the top surface and includes P+ drain
17
b
which is positioned to lie between two areas
14
of field oxide. Source
17
a
lies well outside P− well
18
, also between two areas
14
of field oxide. Adjacent to the source is N+ area
19
to which is shorted thereto through metallic contact
15
. Area
19
serves to provide bulk contact to N− body
12
, providing it with a voltage bias.
The distance L seen in
FIG. 1
defines the channel since it lies beneath polysilicon gate
16
. There is also a layer of gate oxide beneath gate
16
which is not explicitly shown in this figure. It will be noted that L does not extend all the way to the boundary between regions
12
and
18
. This is because, with the application of negative voltage V
d
to the drain, P− depletion region
10
extends outwards, effectively enlarging region
18
, so P channel L does not have to extend all the way to the original region
18
.
Thus the formation of depletion region
10
serves to reduce the on-resistance of the device. The down side of this, however, is that, with the application of relatively low drain voltage, depletion region
10
becomes thick enough to touch P− substrate
11
and punch-through occurs. This effect is illustrated in
FIG. 2
which is a plot of drain current vs. drain voltage for a device of the type illustrated in FIG.
1
. As can be seen, punch-through has occurred at about 10 volts, at which point the drain current is no longer controlled by the gate voltage. The present invention discloses how this problem may be overcome while continuing to retain compatibility with the simultaneous manufacture of N-channel devices and, particularly, without the need to introduce an additional mask into the manufacturing process.
A routine search of the prior art was performed with the following references of interest being found:
In U.S. Pat. No. 5,517,046, Hsing et al. disclose an N-channel LDMOS device with a 2 step doping N− and N+ in an epi layer. Their process and their structure differ from the present invention's process, theirs being a P channel LDMOS device whereas the present invention discloses an N channel device. As a consequence, the N+ buried layer that they teach, while improving on-resistance, has no significant effect on the breakdown voltage.
Other examples of LDMOS devices can be found in U.S. Pat. No. 5,940,700 (Galbiati et al.), U.S. Pat. No. 6,046,473 (Blanchard), and U.S. Pat. No. 6,069,034 (Gregory).
SUMMARY OF THE INVENTION
It has been an object of the present invention to provide a P-type LDMOS device having significantly higher punch-through voltage than similar devices of the prior art.
Another object has been to provide a process for manufacturing said device, said process being fully compatible with the manufacture of a N-type LDMOS device without requiring use of an additional mask.
These objects have been achieved by preceding the epitaxial deposition of N−silicon onto the P−substrate with an additional process step in which a buried N+ layer is formed at the surface of the substrate by ion implantation. This N+ buried layer significantly reduces the width of the depletion layer that extends outwards from the P− well when voltage is applied to the drain thus substantially raising the punch-through voltage.
REFERENCES:
patent: 5517046 (1996-05-01), Hsing et al.
patent: 5525824 (1996-06-01), Himi et al.
patent: 5852314 (1998-12-01), Depetro et al.
patent: 5940700 (1999-08-01), Galbiati et al.
patent: 6046473 (2000-04-01), Blanchard
patent: 6069034 (2000-05-01), Gregory
patent: 6130458 (2000-10-01), Takagi et al.
Huang Chih-Feng
Huang Kuo-Su
Ackerman Stephen B.
Nelms David
Nhu David
Saile George O.
Taiwan Semiconductor Manufacturing Company
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