Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-11-19
2002-07-09
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S368000
Reexamination Certificate
active
06417546
ABSTRACT:
TECHNICAL FIELD
This invention relates to methods of forming field effect transistors, and to field effect transistors and to integrated circuitry.
BACKGROUND OF THE INVENTION
Field effect transistors (FET's) are routinely included in integrated circuitry with a metal-oxide-silicon (MOS) structure. The MOSFET design comprises a pair of diffusion regions, one referred to as a source and the other a drain, each spaced apart within a semiconductive material. This design includes a gate provided adjacent to a separation region between the diffusion regions for imparting an electric field to enable current to flow between the diffusion regions. The substrate separation region adjacent the gate and between the diffusion regions is referred to as a channel. The semiconductive substrate typically comprises silicon having a light conductivity dopant concentration.
To aid in interpretation of the claims that follow, the terms “semiconductive substrate” and “semiconductor substrate” are defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductive substrates described above.
A MOSFET structure is typically fabricated during semiconductor processing by superimposing several layers of conducting, insulating and transistor forming materials. After a series of processing steps, a typical structure might comprise levels of diffusion, polysilicon and metal that are separated by insulating layers. There are generally two types of MOSFETs, namely an n-type transistor and a p-type transistor. These transistors are fabricated within the semiconductor substrate by using either n-type doped silicon that is rich in electrons or p-type doped silicon that is rich in holes. Different dopant ions are utilized for doping the desired substrate regions with the desired concentration of holes or electrons.
The semiconductor industry continually strives to decrease the device size of components in an integrated circuit thereby increasing the overall performance speed. Accordingly, p-type and n-type field effect transistors are routinely included in integrated circuitry fabrication adjacent one another in ever closer proximities. However, as the spacing between the n-type and p-type field effect transistors on a substrate decreased, undesired effects developed. A challenge in fabrication of both transistors is to synchronize the fabrication of the paired p-type and n-type devices so that desired performance is achieved. As a result, device design, and consequently process technology, had to be modified to take these effects into account so that optimum device performance could continue to be obtained.
The gates for each transistor type are routinely fabricated from the same polysilicon layer heavily doped with an n-type material. Such s designs for p-type MOSFETs can include a p-type doped region formed within the channel region between the source/drain. However, as gate widths decrease to below 0.3 microns, this design can allow significant current leakage and increase the difficulty of designing MOSFETs with low threshold voltages to function with low power supplies. A solution is to heavily dope the p-transistor gates with p-type dopant instead of n-type dopant. However, this solution has its own problem. The p-type dopant can diffuse from the gate into the channel to cause significant current leakage between the source/drain regions .
SUMMARY OF THE INVENTION
In accordance with an aspect of the invention, a semiconductor processing method of forming field effect transistors includes forming a first gate dielectric layer over first and second areas of a semiconductor substrate. The first area is configured for forming p-type field effect transistors and the second area is configured for forming n-type field effect transistors. The first gate dielectric layer includes silicon dioxide having nitrogen atoms concentrated therein, the nitrogen atoms being higher in concentration within the first gate dielectric layer at one elevational location as compared to another elevational location. The nitrogen concentration at the one elevational location preferably ranges from 0.1% molar to 10.0% molar. The first gate dielectric layer is removed from over the second area while leaving the first gate dielectric layer over the first area. After removing the first gate dielectric, a second gate dielectric layer is formed over the second area. The second gate dielectric layer includes silicon dioxide proximate an interface of the second gate dielectric layer with the semiconductor substrate and the second gate dielectric layer is substantially void of nitrogen atoms. Next, transistor gates are formed over the first and second gate dielectric layers, and then p-type source/drain regions are formed proximate the transistor gates in the first area and n-type source/drain regions are formed proximate the transistor gates in the second area.
In another aspect of the invention, integrated circuitry includes a semiconductor substrate having an area within which a plurality of n-type and p-type field effect transistors are formed. The respective transistors include a gate, a first gate dielectric layer for the p-type transistors and a second gate dielectric layer for the n-type transistors, and source/drain regions. The first gate dielectric layer includes silicon dioxide having nitrogen atoms therein. The nitrogen atoms are higher in concentration within the first gate dielectric layer at one elevational location as compared to another elevational location. The nitrogen concentration preferably ranges from 0.1% molar to 10.0% molar. The second gate dielectric layer includes silicon dioxide material proximate an interface of the second gate dielectric layer with the semiconductor substrate which is substantially void of nitrogen atoms.
In another aspect of the invention, a semiconductor processing method of forming field effect transistors includes providing a continuous area over a semiconductor substrate for formation of n-type and p-type field effect transistors. The transistors include a gate, a gate dielectric layer and source/drain regions. A predominate portion of the gate dielectric layers of the p-type transistors are formed in the continuous area prior to forming a predominate portion of the gate dielectric layers of the n-type transistors in the continuous area.
REFERENCES:
patent: 4651406 (1987-03-01), Shimizu et al.
patent: 5254489 (1993-10-01), Nakata
patent: 5464792 (1995-11-01), Tseng et al.
patent: 5502009 (1996-03-01), Lin
patent: 5596218 (1997-01-01), Soleimani et al.
patent: 5620908 (1997-04-01), Inoh et al.
patent: 5674788 (1997-10-01), Wristers et al.
patent: 5716864 (1998-02-01), Abe
patent: 5960302 (1999-09-01), Ma et al.
patent: 5972783 (1999-10-01), Arai et al.
patent: 5994749 (1999-11-01), Oda
patent: 6136654 (2000-10-01), Kraft et al.
patent: 6153538 (2000-11-01), An
patent: 6165846 (2000-12-01), Carns et al.
patent: 6200834 (2001-03-01), Bronner et al.
patent: 6225151 (2001-05-01), Gardner et al.
patent: 06302813 (1993-04-01), None
patent: 02001326352 (2001-11-01), None
patent: WO 96/39713 (1996-12-01), None
Kuroi et al., “The Effects of Nitrogen Implantation Into P + Poly-Silicon Gate on Gate Oxide Properties”, 1994 Symposium on VLSI Technology Digest of Technical Papers, pp. 107-108.
Doyle et al., “Simultaneous Growth of Different Thickness Gate Oxides in Silicon CMOS Processing”, IEEE Electron Device Letters, vol. 16, No. 7.
Ko et al., “The Effect of Nitrogen Incorporation Into the Gate Oxide by Using Shallow Implantation of Nitrogen and Drive-in Process”, 1998 IEEE, 0-7803-4932-6/98.
C.T. Liu et al.; “Multiple Gate Oxide Thickness for 2GHz System-on-A-Chip Technologies”; IEEE 1998; pp. 21.2.1-21.2.4.
Trivedi Jigish D.
Wang Zhongze
Yang Rongsheng
Loke Steven
Micro)n Technology, Inc.
Owens Douglas W.
Wells St. John P.S.
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