P-N junction in a vertical memory cell that creates a high resis

Details P-N junction in a vertical memory cell that creates a high resis P-N junction in a vertical memory cell that creates a high resis

1994-04-04

1996-05-28

Hille, Rolf

Active solid-state devices (e.g., transistors, solid-state diode

Non-single crystal, or recrystallized, semiconductor...

Field effect device in non-single crystal, or...

257401, 257350, 257381, 257366, H01L 2976, H01L 31036, H01L 31112

Patent

active

055214010

ABSTRACT:
The invention may be incorporated into a method for forming a vertically oriented semiconductor device structure, and the semiconductor structure formed thereby, by forming a first transistor over a portion of a substrate wherein the first transistor has a gate electrode and a source and drain regions. First and second interconnect regions are formed over a portion of the gate electrode and a portion of the source and drain regions of the first transistor, respectively. A source and drain region of a second transistor is formed over the second interconnect. A Vcc conductive layer is formed over a portion of the source and drain region of the second transistor which is formed over the second interconnect.

REFERENCES:
patent: 3585412 (1971-06-01), Hodges
patent: 3751687 (1973-08-01), Jutzi
patent: 4146902 (1979-03-01), Tanimoto et al.
patent: 4251876 (1981-02-01), McKenney et al.
patent: 4322821 (1982-03-01), Lohstroh et al.
patent: 4558343 (1985-12-01), Ariizumi et al.
patent: 4622575 (1986-11-01), Vora et al.
patent: 4653025 (1987-03-01), Minato et al.
patent: 4814841 (1989-03-01), Masuoka et al.
patent: 5041884 (1991-08-01), Kumamoto et al.
patent: 5103276 (1992-04-01), Shen et al.
patent: 5134581 (1992-07-01), Ishibashi et al.
patent: 5162889 (1992-11-01), Itomi
patent: 5210429 (1993-05-01), Adan
Takato, H., et al., "Impact of Surrounding Gate Transistor (SGT) for Ultra-High-Density LSI's", IEEE Transactions on Electron Devices, vol. 38, No. 3, Mar. 1991.

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