P-domino output latch with accelerated evaluate path

Details P-domino output latch with accelerated evaluate path P-domino output latch with accelerated evaluate path

2006-06-20

2006-06-20

Jeanglaude, Jean Bruner (Department: 2819)

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Field-effect transistor

C326S095000, C326S098000

Reexamination Certificate

active

07064584

ABSTRACT:
An apparatus and method are provided for accelerating the evaluated output of an P-domino latch. The apparatus includes evaluation P-logic, latching logic, keeper logic, and acceleration logic. The evaluation P-logic is coupled to a first N-channel device at a pre-charged node, and is configured to evaluate a logic function based on at least one input data signal. The latching logic is coupled and responsive to a clock signal and the pre-charged node. The latching logic controls the state of a latch node based on the state of the pre-charged node during an evaluation period between a first edge of said clock signal and a second edge of the clock signal. The latching logic otherwise presents a tri-state condition to the latch node. The keeper logic is coupled to the latch node. The keeper logic maintains the state of the latch node when the tri-state condition is presented, and provides a complementary state of the latch node at a complementary latch node. The acceleration logic is coupled and responsive to the pre-charged node and the complementary latch node, and is configured to control the state of an output node.

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