Static information storage and retrieval – Read/write circuit – Including level shift or pull-up circuit
Patent
1995-12-13
1997-02-11
Popek, Joseph A.
Static information storage and retrieval
Read/write circuit
Including level shift or pull-up circuit
365190, 365205, G11C 700
Patent
active
056027850
ABSTRACT:
A pull-up circuit for a DRAM P-channel sense amplifier includes an NMOS transistor and a PMOS transistor connected in parallel with each other between a supply voltage and a pull-up node for the sense amplifier. The transistors are connected to a control circuit that turns on the NMOS transistor during a pull-up cycle and turns on the PMOS transistor only during the initial portion of the pull-up cycle.
REFERENCES:
patent: 4417329 (1983-11-01), Mezawa et al.
patent: 4491741 (1985-01-01), Parker
patent: 4503343 (1985-03-01), Ohuchi
patent: 4601017 (1986-07-01), Mochizuki et al.
patent: 4656612 (1987-04-01), Allan
patent: 4749882 (1988-06-01), Morgan
patent: 4779013 (1988-10-01), Tanaka
patent: 4802129 (1989-01-01), Hoekstra et al.
patent: 4809230 (1989-02-01), Konishi et al.
patent: 4914631 (1990-04-01), Johnson et al.
patent: 4924442 (1990-05-01), Chen et al.
patent: 5245579 (1993-07-01), Ohta
patent: 5250854 (1993-10-01), Lien
patent: 5276647 (1994-01-01), Matsui et al.
patent: 5285407 (1994-02-01), Gale et al.
patent: 5438543 (1995-08-01), Yoon
patent: 5453951 (1995-09-01), Proebsting
Micro)n Technology, Inc.
Popek Joseph A.
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