Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-11-22
2001-08-21
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S329000, C257S330000, C257S335000
Reexamination Certificate
active
06278155
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of producing the same.
2. Related Arts
When connecting a power metal oxide semiconductor field effect transistor (a power MOSFET) to a load, there are two types of connection, i. e., a high side connection shown in
FIG. 28 and a
low side connection shown in FIG.
29
. In the high side connection, a power MOSFET
41
is disposed between a power supply V
DD
and a load
40
. In this connection, even if the load
40
itself is short-circuited to the earth, the power MOSFET
41
can control current flowing through the load. Therefore, in many cases, the high side connection is adopted because of high reliability.
Especially, a p-channel power MOSFET is suitable for the high side connection, because the p-channel power MOSFET is turned ON when a gate electric potential is controlled to be negative with respect to a source electric potential. However, the ON resistance of the p-channel power MOSFET is two or three times higher than that of an n-channel power MOSFET if the chip sizes thereof are the same. To obtain low ON resistance of the p-channel power MOSFET, it is effective to increase the chip size of the MOSFET. However, large chip size results in high cost. Because of this, at present, there is a case where the n-channel power MOSFET having low ON resistance is used in the high side connection as shown in FIG.
30
. In the case where the n-channel power MOSFET is arranged in the high side connection, it is necessary to employ a voltage rising circuit
42
for raising the gate electric potential of the n-type channel power MOSFET, because the n-type channel power MOSFET is not turned ON unless a gate electric potential is higher than a source electric potential. The provision of such voltage rising circuit
42
results in high cost on its system design and the like. Accordingly, in the case where the n-channel power MOSFET is more advantageous in cost than that of the p-channel power MOSFET having high ON resistance, the n-channel power MOSFET is likely to be employed.
Here, if the p-type channel power MOSFET having low ON resistance is obtained, since the p-channel power MOSFET does not need the voltage rising circuit or the like as shown in
FIG. 28
, a power MOSFET high side switch having a simple system structure can be realized.
Recently, an n-channel power MOSFET, in which resistance component associated with junction field effect transistor (JFET) parasitically caused in the power MOSFET is lowered by forming a groove in a surface of a silicon substrate, has been proposed. In addition, in this n-channel power MOSFET, a semiconductor fine processing technique is applied to reduce a size of a unit cell of the power MOSFET. As a result, degree of integration is increased, resulting in decrease of the ON resistance.
For example, JP-A-56-96865 and JP-A-60-28271 an. disclose the n-channel power MOSFET utilizing a local oxidation of silicon (LOCOS) technique. More concretely, a local oxide (LOCOS) layer is formed on a surface of a silicon substrate, and then, double diffusion layers are formed by utilizing the LOCOS layer as a diffusion mask. Thereafter, the LOCOS layer is removed to form a silicon groove, and a gate oxide layer and a gate electrode are formed on the silicon groove.
To form the n-channel power MOSFET, arsenic (As) ions are usually implanted to form a shallow source diffusion layer which is one of the double diffusion layers.
By utilizing the above mentioned technique, the unit cell size of the n-channel power MOSFET is reduced and simultaneously the ON resistance is lowered.
However, in the case where the above mentioned structure is applied to a p-channel power MOSFET, there arise the following problems.
That is to say, as impurities for forming a source diffusion layer of the p-channel power MOSFET, boron (B) ions having a diffusion coefficient larger than that of As ions are utilized in place of As ions.
In general, after forming the source diffusion layer, there exist some heat treatment steps which inevitably cause further diffusion of the source diffusion layer. In particular, in the case of the p-channel power MOSFET with the groove, because the diffusion coefficient of B ions is large, a diffusion depth of B ions becomes deep during the heat treatment steps such as gate oxidation, gate formation, and the like. As a result, a thickness of a channel region becomes small, giving rise to a punch through phenomenon.
To prevent the punch through phenomenon, it is effective to reduce the impurity concentration of boron ions in the source diffusion layer. Accordingly, the diffusion depth of boron ions becomes shallow, resulting in a shallow-junction. In this case, however, the contact resistance between the source diffusion layer and a source electrode made of aluminum or the like increases, so that the ON resistance of the p-channel power MOSFET increases as well.
SUMMARY OF THE INVENTION
The present invention has been made in view of the above mentioned problems and objects of the present invention are to provide a semiconductor device, in particular a p-channel MOSFET, having a low ON resistance and capable of preventing a punch through phenomenon, and to provide a method of producing the same.
According to the present invention, a semiconductor device has a source region composed of a first source region and a second source region. The second source region is formed in a surface of the first source region to have a higher impurity concentration than that of the first source region. Further, a source electrode is formed to contact with the second source region.
Accordingly, because the contact resistance between the source electrode and the source region is decreased owing to the second source region having the higher impurity concentration, the ON resistance of the semiconductor device can be lowered. In addition, the impurity concentration of the first source region can be reduced irrespective of the contact resistance, so that a diffusion depth of the first source region can be made shallow. As a result, a channel length enough to prevent a punch through phenomenon is obtained. Thus, both prevention of the punch through phenomenon and decrease in the ON resistance can be realized at the same time.
Preferably, after forming the gate electrode on the semiconductor substrate through a gate insulation layer, the second source region is formed on the first source region by implantation of impurities. In this case, after forming the second source region, it is not necessary to expose the semiconductor device to a high temperature atmosphere. Therefore, the diffusion of the impurities in the second source region is prevented after forming itself, thereby keeping the source region shallow.
More preferably, the gate electrode is made of polycrystalline silicon, and is formed by implanting impurities into a non-doped polycrystalline silicon layer. In this case, the implantation of the impurities for forming the gage electrode and the implantation of the impurities for forming the second source region may be performed at the same time. As a result, the manufacturing process can be simplified.
To the contrary, after implanting the impurities to form the gate electrode, a mask layer may be formed on the gate electrode, and thereafter, the second source region may be formed by the implantation of the impurities. In this case, the mask layer prevents the impurities from invading the gate electrode in the process of forming the second source region, so that the implantation of the impurities into the gate electrode and into the second source region can be controlled, respectively. As a result, for example, when the polycrystalline silicon electrode is used as a resistor, the resistance thereof can be easily controlled to a desired value.
The semiconductor substrate may have a groove having sidewalls composed of the channel well region and the source region.
The present invention can be applied to a p-channel type transistor.
Other objects and fea
Kataoka Mitsuhiro
Okabe Yoshifumi
Tomatsu Yutaka
Chaudhuri Olik
Denso Corporation
Pham Hoai
Pillsbury & Winthrop LLP
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