P-channel MOS transistor and fabrication process thereof

Details P-channel MOS transistor and fabrication process thereof P-channel MOS transistor and fabrication process thereof

2007-08-28

2007-08-28

Smith, Zandra V. (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S616000, C257S401000

Reexamination Certificate

active

11114047

ABSTRACT:
A p-channel MOS transistor includes a strained SOI substrate formed of a SiGe mixed crystal layer and a strained Si layer formed on the SiGe mixed crystal layer via an insulation film, a channel region being formed in the strained Si layer, a gate electrode formed on the strained Si layer in correspondence to the channel region via a gate insulation film, and first and second p-type diffusion regions formed in the strained Si layer at respective first and second sides of the channel region, wherein the strained Si layer has first and second sidewall surfaces respectively at the first and second sides thereof, a first SiGe mixed crystal region being formed epitaxially to the SiGe mixed crystal layer in contact with the first sidewall surface, a second SiGe mixed crystal region being formed epitaxially to the SiGe mixed crystal layer in contact with the second sidewall surface, the first and second SiGe mixed crystal regions being in lattice matching with the strained silicon layer respectively at the first and second sidewall surfaces.

REFERENCES:
patent: 6603156 (2003-08-01), Rim
patent: 6621131 (2003-09-01), Murthy et al.
patent: 8-167718 (1996-06-01), None
patent: 2003-179157 (2003-06-01), None
patent: 2004-31753 (2004-01-01), None

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