P-channel electrically alterable non-volatile memory cell

Details P-channel electrically alterable non-volatile memory cell P-channel electrically alterable non-volatile memory cell

2007-02-20

2007-02-20

Dang, Phuc T. (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S302000

Reexamination Certificate

active

10962288

ABSTRACT:
A nonvolatile memory cell is provided. The memory cell comprises a storage transistor and an injector in a semiconductor substrate of a p-type conductivity. The injector comprises a first region of the p-type conductivity and a second region of an n-type conductivity. The storage transistor comprises a source, a drain, a channel, a charge storage region, and a control gate. The source and the drain have the p-type conductivity and are formed in a well of the n-type conductivity in the substrate with the channel of the well defined therebetween. The charge storage region is disposed over and insulated from the channel by a first insulator. The control gate is disposed over and insulated from the charge storage region by a second insulator. Further provided are methods operating the memory cell, including means for injecting electrons from the channel through the first insulator onto the charge storage region and means for injecting holes from the injector through the well through the channel through the first insulator onto the charge storage region.

REFERENCES:
patent: 4816883 (1989-03-01), Baldi
patent: 4957877 (1990-09-01), Tam et al.
patent: 5106772 (1992-04-01), Lai
patent: 5822242 (1998-10-01), Chen
patent: 5877524 (1999-03-01), Oonakado et al.
patent: 5966329 (1999-10-01), Hsu et al.
patent: 6140676 (2000-10-01), Lancaster
patent: 6172397 (2001-01-01), Oonakado et al.
patent: 6631087 (2003-10-01), Di Pede et al.
patent: 6791883 (2004-09-01), Swift et al.
U.S. Appl. No. 10/107,440, filed Oct. 3, 2002, Ohba et al.
U.S. Appl. No. 10/606,164, filed Apr. 1, 2004, Cappelletti et al.
K. Naruke et al., “Stress Induced Leakage Current Limiting to Scal Down EEPROM Tunnel Oxide Thickness”, IEDM Technical Digest, p. 424-427, 1988.
C. Diorio, “A p-Channel MOS Synapse Transistor with Self-Convergent memory Writes”, IEEE Trans. on Electron Devices, vol. 47, pp. 464-472, 2000.
T. Ohnakado et al., “Novel Electron Injection Method Using Band-to-Band Tunneling Induced Hot Electron (BBHE) for Flash Memory with a p-channel . . . ”, IEDM Tech. Dig.,p. 279, 1995.
Nishida et al, “Oxide field and thickness dependence of trap generation in 9-30 nm dry and dry/wet/dry oxides”, J. Appl. Phys., vol. 69, pp. 3986-3994, 1991.
U.S. Appl. No. 09/945,398, filed Feb. 21, 2002, Leonard Forbes.
U.S. Appl. No. 09/515,630, filed Jan. 31, 2002, Leonard Forbes.
U.S. Appl. No. 09/818,296, filed Oct. 11, 2001, Lin et al.

Affiliated with

Also associated with

Rating

P-channel electrically alterable non-volatile memory cell does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with P-channel electrically alterable non-volatile memory cell, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and P-channel electrically alterable non-volatile memory cell will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3828090