Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Insulative material deposited upon semiconductive substrate
Reexamination Certificate
1998-05-29
2001-06-12
Trinh, Michael (Department: 2822)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Insulative material deposited upon semiconductive substrate
C438S624000, C438S424000, C438S439000
Reexamination Certificate
active
06245691
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to ozone-TEOS thermal chemical vapor deposition (CVD) methods for forming within microelectronics fabrications silicon oxide dielectric layers. More particularly, the present invention relates to ozone-TEOS thermal chemical vapor deposition (CVD) methods for forming within microelectronics fabrications silicon oxide dielectric layers formed with attenuated surface sensitivity with respect to thermally oxidized silicon substrate layers.
2. Description of the Related Art
Integrated circuit microelectronics fabrications are formed from semiconductor substrates within and upon which are formed integrated circuit devices. The integrated circuit devices are connected internally and externally to the semiconductor substrates upon which they are formed through patterned integrated circuit conductor layers which are separated by integrated circuit dielectric layers.
As integrated circuit microelectronics fabrication integration levels have increased and integrated circuit device and patterned conductor layer dimensions have decreased, it has become more prevalent in the art of integrated circuit microelectronics fabrication to employ trench isolation methods, such as but not limited to shallow trench isolation (STI) methods and recessed oxide isolation (ROI) methods, to form trench isolation regions within a semiconductor substrate in order to separate the active regions of the semiconductor substrate within and upon which are formed integrated circuit devices.
Such shallow trench isolation (STI) methods and recessed oxide isolation (ROI) methods are desirable within integrated circuit microelectronics fabrications since shallow trench isolation (STI) methods and recessed oxide isolation (ROI) methods provide trench isolation regions which are nominally co-planar with a surface of an adjoining active region of a semiconductor substrate. Such nominally co-planar trench isolation regions and adjoining active regions of a semiconductor substrate generally optimize an attenuated depth of focus typically achievable with an advanced photoexposure apparatus employed when forming advanced integrated circuit microelectronics devices and advanced patterned conductor layers within an advanced integrated circuit microelectronics fabrication.
While shallow trench isolation (STI) methods and recessed oxide isolation (ROI) methods are thus desirable when forming trench isolation regions within advanced integrated circuit microelectronics fabrications, shallow trench isolation (STI) methods and recessed oxide isolation (ROI) methods are nonetheless not entirely without problems within advanced integrated circuit microelectronics fabrications. In particular, it is often difficult to form when employing shallow trench isolation (STI) methods within integrated circuit microelectronics fabrications shallow trench isolation regions which simultaneously possess superior gap filling properties, superior bulk physical properties and enhanced deposition rates which in the aggregate provide shallow trench isolation regions with optimal properties within advanced integrated circuit microelectronics fabrications.
Of the dielectric layer deposition methods potentially applicable for forming shallow trench isolation regions when employing shallow trench isolation (STI) methods within integrated circuit microelectronics fabrications, atmospheric pressure thermal chemical vapor deposition (APCVD) methods and sub-atmospheric pressure thermal chemical vapor deposition (SACVD) methods employing ozone as an oxidant source material and tetraethylorthosilicate (TEOS) as a silicon source material (hereinafter, in general, “ozone-TEOS thermal chemical vapor deposition (CVD) methods”) are particularly desirable due to the superior gap filling properties of shallow trench isolation regions formed employing those ozone-TEOS thermal chemical vapor deposition (CVD) methods. Such ozone-TEOS thermal chemical vapor deposition (CVD) methods typically preclude plasma activation due to the increased reactor chamber pressures at which they are undertaken. While ozone-TEOS thermal chemical vapor deposition (CVD) methods do typically provide shallow trench isolation regions formed with superior gap filling properties, ozone-TEOS thermal chemical vapor deposition (CVD) methods typically nonetheless also provide shallow trench isolation regions with inferior bulk properties (as typically evidenced by increased aqueous hydrofluoric acid etch rate) and with attenuated deposition rates upon thermal silicon oxide trench liner layers formed through thermal oxidation of silicon semiconductor substrates within which are formed those shallow trench isolation regions employing those ozone-TEOS thermal chemical vapor deposition (CVD) methods.
It is thus towards the goal of forming within integrated circuit microelectronics fabrications shallow trench isolation regions while employing ozone-TEOS thermal chemical vapor deposition (CVD) methods to provide shallow trench isolation regions simultaneously possessing: (1) enhanced gap filling properties; (2) enhanced bulk properties, such as but not limited to aqueous hydrofluoric acid wet chemical etch rate; and (3) attenuated surface sensitivity of the shallow trench isolation regions when formed upon thermal silicon oxide trench liner layers formed through thermal oxidation of silicon semiconductor substrates, that the present invention is more specifically directed. In a more general sense, the present invention is directed towards forming within microelectronics fabrications which are not necessarily integrated circuit microelectronics fabrications silicon oxide dielectric layers formed employing ozone-TEOS thermal chemical vapor deposition (CVD) methods, where the silicon oxide dielectric layers simultaneously possess: (1) enhanced gap filling properties: (2) enhanced bulk properties; and (3) attenuated surface sensitivity of the silicon oxide dielectric layers with respect to other microelectronics substrate layers which may include, but are not limited to, thermal silicon oxide dielectric layers formed through thermal oxidation of a silicon substrate layer.
Various aspects of ozone-TEOS thermal chemical vapor deposition (CVD) methods for forming silicon oxide dielectric layers within microelectronics fabrications have been disclosed in the arts of microelectronics fabrication.
For example, Chang et al., in ULSI Technology, McGraw-Hill (1997), pp. 415-419 discloses in general various aspects of ozone-TEOS atmospheric pressure thermal chemical vapor deposition (APCVD) methods and ozone-TEOS sub-atmospheric pressure thermal chemical vapor deposition (SACVD) methods for forming silicon oxide dielectric layers within integrated circuit microelectronics fabrications.
In addition, Kwok et al., in U.S. Pat. No. 5,271,972, discloses a method for attenuating a surface sensitivity of a first silicon oxide dielectric layer formed through either: (1) an ozone-TEOS atmospheric pressure thermal chemical vapor deposition (APCVD) method; or (2) an ozone-TEOS sub-atmospheric pressure thermal chemical vapor deposition (SACVD) method, when the first silicon oxide dielectric layer is formed upon a second silicon oxide dielectric layer formed employing a plasma enhanced chemical vapor deposition (PECVD) method. The method employs a sequential ramping down of a plasma power during the last few seconds of forming the second silicon oxide dielectric layer while employing the plasma enhanced chemical vapor deposition (PECVD) method, to thereby form an interstitial silicon oxide layer upon the surface of the second silicon oxide dielectric layer, where the interstitial silicon oxide layer provides the second silicon oxide dielectric layer with attenuated surface sensitivity for forming upon the second silicon oxide dielectric layer the first silicon oxide dielectric layer.
Similarly with Kwok et al., Nguyen et al., in U.S. Pat. No. 5,356,722, also discloses a method for attenuating a surface sensitivity of a first silicon oxide diel
Jang Syun-Ming
Yu Chen-Hua
Ackerman Stephen B.
Guerrero Maria
Saile George O.
Szecsy Alek P.
Taiwan Semiconductor Manufacturing Company
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