Oxygen implant self-aligned, floating gate and isolation...

Details Oxygen implant self-aligned, floating gate and isolation... Oxygen implant self-aligned, floating gate and isolation...

2000-05-11

2001-11-13

Booth, Richard (Department: 2812)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S316000, C257S506000, C257S513000

Reexamination Certificate

active

06316804

ABSTRACT:

TECHNICAL FIELD
The present invention relates to integrated circuits and fabrication techniques for forming field oxide (FOX) regions on the integrated circuit substrate. More particularly, the present invention relates to fabrication techniques for forming field oxide regions that facilitate forming self-aligned, floating gates on the integrated circuit substrate.
BACKGROUND OF THE INVENTION
The processes for fabricating MOS (metal oxide semiconductors) devices includes process steps for forming isolation regions that contain dielectric materials that provide the necessary protection for assuring proper function of the formed electronic integrated circuits, such as by minimizing leakage currents between individual devices. The various processes includes LOCOS which is an abbreviation for localized oxidation of silicon. The LOCOS process typically begins by depositing a silicon nitride layer over a silicon dioxide layer to a thickness in the range of 0.05 &mgr;m. to 0.20 &mgr;m. The silicon nitride layer is typically deposited using low-pressure chemical vapor deposition (LPCVD) techniques. A photoresist mask layer, comprising any appropriate commercially available photoresist material is then deposited over the silicon nitride layer and patterned by methods known in the industry. After etching the unprotected silicon nitride portions delineated by the photoresist mask and stripping the photoresist mask, a plurality of spaced apart silicon nitride regions remain on the substrate, see generally FIG.
1
. The silicon nitride regions prevent oxidation of the underlying regions during a thermal oxidation process used to grow oxide isolation regions, see generally FIG.
2
. The thickness of the grown oxide isolation regions is on the order of 0.10 &mgr;m to 0.50 &mgr;m. Subsequent to the formation of the oxide isolation regions the silicon nitride and silicon dioxide layer regions are removed by selectively wet etching to expose the active region which will be used to form the various integrated circuit components. The wet etching is typically done using hot phosphoric acid to first selectively etch the silicon nitride layer, then by dipping the substrate in a hydrofluoric acid (HF) dip to primarily etch away the silicon thin dioxide layer and prepare a clean surface upon which to form a uniform thin oxide. The process continues by growing a thin oxide layer that primarily covers the exposed active region, but also adds to the thickness of the previously grown oxide isolation regions. By example, the process further continues by deposition of a polysilicon layer over the oxide isolation regions and the thin oxide layer.
FIG. 3
shows a substrate structure after having applied a photoresist mask for defining the polysilicon layer over the active region and thus forming a floating gate region.
As seen from the foregoing, formation of the oxide isolation region, in accordance with prior art techniques, involves an etching process that removes the oxide and silicon nitride in regions adjacent to those that will protect the active substrate regions during the subsequent LOCOS process. The prior art process involves a substantial number of fabrication steps that impact the cost of the product. Thus, a need is seen to exist for a method of forming the oxide isolation regions without etching and that minimizes the fabrication steps to produce semiconductor devices. Further, in order to maximize the number of devices that can fit into a given area, it is desirable to make floating gates as small as possible. For good electrical properties this means that the floating gates should be just large enough to cover the active areas beneath them. However, in practice, and since the floating gate and the active area structures are formed in two separate masking steps, the floating gate mask can be misaligned with respect to the active area. As a consequence, the floating gate has to be made larger than the ideal minimum size to account for manufacturing tolerances in aligning the two masking layers, as well as for size variations in the floating gate and active region that occur as a natural part of the masking process.
Accordingly, a primary object of the present invention is to provide a method for forming oxide isolation regions without etching and that minimizes the fabrication steps to produce semiconductor device, such as semiconductor devices having a floating gate structure.
Accordingly, another primary object of the present invention is to provide a method that defines a floating gate and active area simultaneously with one mask and thereby allowing formation of a minimum-sized floating gate structure.
BRIEF SUMMARY OF THE INVENTION
Accordingly, the foregoing object is accomplished by providing a semiconductor apparatus and fabrication method for forming oxide isolation regions in a semiconductor substrate for use in forming self-aligned floating gate MOS structures, or other semiconductor devices. The method includes providing a semiconductor substrate member prefabricated having an oxide layer, a polysilicon layer and a plurality of silicon nitride layer portions fabricated on the polysilicon layer. The spaced apart silicon nitride layer not only delineate, by covering, active regions for forming the self-aligned floating gate MOS structures, they also delineate portions of the silicon dioxide layer and portions of said polysilicon layer that are unprotected by the plurality of spaced apart silicon nitride layer portions. The method further includes the step of implanting oxygen O
2
ions into the substrate, in particular the regions that are unprotected by the silicon nitride. The implanting energy and concentration of oxygen ions penetrates the unprotected portions of the silicon dioxide layer and portions of the polysilicon layer to form the isolation regions in the underlying silicon substrate. After removing the silicon nitride layer portions, and exposing the polysilicon layer portions, the implanted structure is annealed and made ready for completing the self-aligned floating gate MOS structures, or other semiconductor structure on the conductive material regions.
Other features of the present invention are disclosed or apparent in the section entitled: DETAILED DESCRIPTION OF THE INVENTION.


REFERENCES:
patent: 5015601 (1991-05-01), Yoshikawa
patent: 5599727 (1997-02-01), Hakozaki et al.
patent: 5731237 (1998-03-01), Sato
patent: 5851881 (1998-12-01), Lin et al.
patent: 6013551 (2000-01-01), Chen et al.

Affiliated with

Also associated with

Rating

Oxygen implant self-aligned, floating gate and isolation... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Oxygen implant self-aligned, floating gate and isolation..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Oxygen implant self-aligned, floating gate and isolation... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2605351