Oxide trench structure for polysilicon gates and interconnects

Details Oxide trench structure for polysilicon gates and interconnects Oxide trench structure for polysilicon gates and interconnects

1983-04-18

1985-03-12

Weisstuch, Aaron

Metal working

Method of mechanical manufacture

Assembling or joining

29576W, 29576B, 29577C, 148 15, H01L 2126

Patent

active

045036012

ABSTRACT:
Disclosed is a manufacturing method of forming silicon gate, self-aligned MOS-type devices having submicron dimensions. After forming the gate from a highly doped polysilicon layer using a mask, the structure is subjected to a low temperature (700-750 degrees C.) thermal oxidation. Due to enhanced oxidation rate of doped silicon surfaces, a very thick oxide layer over the polysilicon gate sidewalls and a relatively thin oxide layer over the source-drain regions of the substrate are formed. The mask over the polysilicon and the oxide layer over the source-drain regions is removed and source-drain implantation is accomplished followed by selective deposition of metal (e.g. tungsten) over the source-drain regions and the polysilicon gate.
In an alternative embodiment of this process, after forming the highly doped polysilicon gate using a mask, lightly doped source-drain regions which are self-aligned and in registry with the gate are formed by ion implantation. Then, low temperature thermal oxidation is accomplished growing a thick oxide over the polysilicon gate sidewalls and a thin oxide over the source-drain regions. The mask over the gate and the thin oxide over the source-drain regions is removed and by ion implantation heavily doped source-drain regions are formed in the previously formed lightly doped source-drain regions not masked by the polysilicon sidewall oxide. Selective deposition of a metal is then accomplished over the source-drain regions of the silicon substrate and the polysilicon gate.

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Takeda et al., "Submicrometer MOSFET Structure for Minimizing Hot-Carrier Generation," IEEE Transaction on Electron Devices, vol. ED-29, No. 4, pp. 611-618, Apr. 1982.
Ogura et al., "Design and Characteristics of the Lightly Doped Drain-Source (LDD) Insulated Gate Field-Effect Transistor," Journal of Solid State Circuits, vol. SC-15, No. 4, pp. 424-432, Aug. 1980.
H. Sunami and M. Koyanagi, "Selective Oxide Coating of Silicon Gate (SELOCS)", Japanese Journal of Applied Physics, vol. 18, (1979), Supplement 18-1, pp. 255-260.

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