Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Patent
1998-02-17
2000-08-08
Fahmy, Wael
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
438440, 438769, H01L 2176
Patent
active
061001600
ABSTRACT:
A structure and method for slowing down the etch rate of CVD oxide film 230 relative to the etch rate of thermal oxide 210 to prevent excessive removal of CVD oxide 230 during the stripping of the thermal oxide 210. Nitridation has been shown to be effective at retarding the etch rate of oxides. Therefore, nitridation of the CVD oxide 230 decreases the amount of oxide loss when thermal oxide 210 is etched. Nitridation of the wafer surface can be performed either before or after the nitride 200 removal step in standard process flows. In processes that use a densified CVD oxide 230, the densification of the CVD film 230 can be performed in an ambient that incorporates nitrogen in the film to significantly decrease the etch rate of the isolation oxide 230. Due to the porosity and the increased hydrogen content of the CVD oxide 230 as compared to the hydrogen content of thermal oxide 210, the nitrogen is incorporated more rapidly in the CVD oxide 230 than in the exposed thermal oxide 210. Therefore, the etch rate of the CVD 230 relative to the thermal oxide 210 (e.g. the selectivity) can approach one or even less than one.
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Hisham Z. Massoud, he Onset of the Thermal Oxidation of Silicon from Room Temperature to 1000 c., MicroElectronic Engineering, pp. 109-116, Dec. 1995.
Brady III W. James
Coleman William David
Fahmy Wael
Telecky Jr. Frederick J.
Texas Instruments Incorporated
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