Overvoltage-tolerant self-biasing CMOS output buffer

Details Overvoltage-tolerant self-biasing CMOS output buffer Overvoltage-tolerant self-biasing CMOS output buffer

1995-12-28

1997-06-03

Hudspeth, David R.

Electronic digital logic circuitry

Interface

Supply voltage level shifting

326 34, H03K 19003

Patent

active

056358601

ABSTRACT:
An overvoltage-tolerant self-biasing input/output buffer circuit having a p-channel field-effect transistor ("FET"), a first n-channel FET and a biasing circuit for biasing the body of the p-channel FET so as to prevent forward-biasing of the of the p-channel FET. The p-channel FET has a source connected to a first voltage, a gate connected to a first input, a drain connected to an output, and the body connected to a node. The first n-channel FET has a drain connected to the output, a gate connected to a second input, a body connected to a second voltage, and a source connected to the second voltage. The biasing circuit includes a second n-channel FET and a third n-channel FET. The second n-channel FET has a source and a gate connected to the first voltage, a drain connected to the node, and a body connected to the second voltage. The third n-channel FET has a drain connected to the node, a gate and a source connected to the output, and a body connected to the second voltage.

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Brian C. Martin, Tips for Straddling the 3-V to 5-V Fence, Electronic Design, Apr. 4, 1994, pp. 67-72.
Marcel J. M. Pelgrom and E. Carel Dijkmans, A 3/5 V Compatible I/O Buffer, IEEE Journal of Solid-State Circuits, vol. 30, No. 7, Jul. 1995, pp. 823-825.

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