Overvoltage tolerant intergrated circuit output buffer

Details Overvoltage tolerant intergrated circuit output buffer Overvoltage tolerant intergrated circuit output buffer

1995-01-31

1996-10-29

Westin, Edward P.

Electronic digital logic circuitry

Interface

Supply voltage level shifting

326 27, 326 21, H03K 1716

Patent

active

055700438

ABSTRACT:
An overvoltage tolerant output buffer circuit for coupling an integrated circuit (IC) to external electrical apparatus by way of a contact pad or other input/output connection. An overvoltage protection circuit is provided to bias the semiconductor or well region containing the pull-up driving transistors of the output buffer so as to reduce current injected to the supply rail of the IC from the contact pad during an overvoltage condition. The protection circuit is arranged to bias the substrate on the basis of a potential difference between the supply rail and the contact pad so that neither of the supply rail and contact pad substantially exceeds the potential of the substrate. Circuitry is also provided to block signals from being passed to the buffer circuit from other circuits on the IC, and for preventing a gate-source potential difference from being applied to the pull-up driving transistors during the overvoltage condition.

REFERENCES:
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Daniel W. Dobberpuhl et al., "A 200-MHz 64-b Dual-Issue CMOS Microprocessor" IEEE Journal of Solid-State Circuits, vol. 27, No. 11, pp. 1555-1567 (Nov. 1992).

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