Overvoltage tolerant integrated circuit input/output interface

Details Overvoltage tolerant integrated circuit input/output interface Overvoltage tolerant integrated circuit input/output interface

1998-10-26

2001-04-24

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Interface

Current driving

C326S081000, C326S080000

Reexamination Certificate

active

06222387

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to an overvoltage tolerant buffer circuit which is suitable for driving an integrated circuit I/O (input/output) connection and, more particularly, to the overvoltage detection portion of the buffer circuit.
BACKGROUND
An increase in the number of fabrication processes available for manufacturing integrated circuits has lead to an increased diversity in operating conditions under which the integrated circuits perform. For example, the range of supply voltages, switching voltages, input and output voltages can vary as between integrated circuits fabricated by different processes. In order for an integrated circuit to be compatible with circuits manufactured using a different process, it may therefore be necessary for the integrated circuit to be tolerant of voltages on the I/O connections thereof which are different from voltages which may be received from a circuit manufactured using the same fabrication process.
One particular problem which has been encountered is the application of a voltage to an I/O connection which is higher that the supply voltage for the integrated circuit. This is referred to as an overvoltage condition at the I/O connection. For example, complimentary metal oxide semiconductor (CMOS) circuits can be manufactured to operate on a supply voltage (Vcc) of 3.3 volts (where the rail-to-rail voltage swing is 3.3 volts), while many other circuits utilize a 5 volt supply and can thus be expected to produce an output in the region of 5 volts. If a 3.3 volt CMOS circuit receives an input of 5 volts at an I/O connection thereof (an overvoltage condition), difficulties can be encountered within an input/output buffer circuit of the 3.3 volt CMOS circuit. In particular, an undesirable large leakage current from the I/O connection through the input/output buffer of the 3.3 volt CMOS circuit may arise as a result of the overvoltage condition. Additionally, latch up of the CMOS circuit can OCCuI as a result of the overvoltage condition. Both of these phenomena are detrimental to the operation of the CMOS circuit and can, in extreme circumstances, result in destruction of the circuit.
To illustrate the dangers associated with overvoltage conditions, consider the simplified CMOS output buffer circuit
2
shown in FIG.
1
. Output buffer
2
drives an I/O connection
4
, such as a contact pad of an integrated circuit (IC), which contains the buffer
2
, in accordance with signals received on control lines
6
. As shown, output buffer
2
includes a PMOS pull-up transistor
8
which couples the I/O pad
4
, by way of an output line
10
, to a supply voltage line
12
(Vcc). An NMOS pull-down transistor
14
couples the I/O pad
4
to another supply voltage such as Vss or ground (GND). In operation, the pull-up and pull-down transistors
8
,
14
are controlled by way of the control lines
6
so as to selectively couple the I/O pad
4
to the supply rail
12
or GND, which enables the output voltage to swing between GND (e.g., zero volts) and Vcc (the supply voltage, e.g., 3.3 volts). In order for the output buffer
2
to drive the I/O pad
4
all the way to the positive supply voltage Vcc, the pull-up transistor
8
must be a PMOS type transistor in order to avoid the undesirable voltage drop which would occur if an NMOS type transistor were used for this function.
In a CMOS fabrication process, the PMOS and NMOS transistors which make up the integrated circuit are typically fabricated in separate regions of the silicon substrate, the P-type transistors in an N-type region, and the N-type transistors in a P-type region. One way in which this is achieved is to dope the semiconductor wafer with a P-type majority carrier in which the N-type transistors can be formed, and to form discrete N-type “well”, regions in which the P-type transistors are fabricated, which is referred to as an n-well CMOS process. Typically the n-well substrate regions are biased to the supply voltage of the integrated circuit, which promotes proper operation of the transistors formed therein.
An equivalent circuit
20
of the output buffer circuit is shown in
FIG. 2
, which illustrates the result of the application of an overvoltage to the I/O pad
4
. An electrical apparatus
22
is shown connected to the output buffer
2
by way of the I/O pad
4
. The apparatus
22
may, for example, be another integrated circuit which operates at a higher supply voltage (e.g., 5 volts) than the IC which contains output buffer
2
. When the electrical apparatus
22
raises the potential of output line
10
above the supply voltage Vcc of the output buffer
2
, the drain terminal of the pull-up transistor
8
is raised above the potential of both the gate terminal thereof and the substrate region in which the transistor is formed. This causes the PMOS pull-up transistor
8
to turn on, which creates a current path from the output line
10
to the supply line
12
, and also causes the drain-substrate diode of the transistor
8
to be forward biased, creating another current path from the output line
10
to the Vcc supply line
12
. These current paths are indicated by dashed lines (I) in FIG.
2
. This situation, at best, stops the voltage at the I/O pad
4
from rising much above the Vcc supply voltage of the IC which contains output buffer
2
, but can also cause CMOS latch-up in this IC because of the injected current.
A similar situation may occur during “hot”, or “live insertion”. In this case, the I/O connections of an integrated circuit device are assumed to be conditioned (i.e., non-zero voltage) before the power supply is connected thereto. Even though the voltage applied to the I/O connections may not be an overvoltage in the sense of being greater than the operating supply voltage of the device, the instantaneous voltage at the I/O connections is nevertheless greater than the voltage applied to the power supply line when power is connected (ramped) to the device. In this instance, a major concern is latch-up if excessive current is injected from the I/O connection.
Bud hold circuits may suffer from similar effects. For example,
FIG. 3
shows a bus hold circuit
30
which includes a two-inverter latch. A bus hold circuit is designed to prevent a bus from floating to an undefined state when all of the devices connected to the bus are in a high impedance state. Without the use of such a circuit, the input buffers of devices connected to the bus could produce false transitions and may also dissipate unacceptably high currents. The bus hold circuit
30
includes a CMOS inverter
34
connected in a feedback path around another CMOS inverter
36
. An input to CMOS inverter
36
is connected to I/O pad
4
. CMOS inverter
34
includes a PMOS transistor
38
connected in series with an NMOS transistor
40
, the source of the PMOS transistor
38
being connected to an on-chip supply voltage, e.g., a 3.3 volt supply (Vcc). In operation, the I/O pad
4
is driven by a bus and therefore the voltage which appears at I/O pad
4
will correspond to whatever voltage is on the bus (e.g., 5V). Bus hold circuit
30
is designed to allow the bus to drive the input of inverter
36
and hold its value of logic high or low at the output of inverter
36
. When an I/O driver of the bus is then tri-stated, the bus hold inverter
34
will maintain the logic level of the bus, so that the bus state does not become undefined.
To sustain a bus hold, CMOS inverter
34
must be connected to I/O pad
4
. If
5
volts is applied to a bus hold circuit operating from a 3.3 volt supply voltage (Vcc), a parasitic n-well diode (not shown, but similar to that described above) associated with the PMOS transistor
38
of CMOS inverter
34
becomes forward biased and injects current into Vcc. The n-well diode turns on when the pad voltage rises above Vcc. Furthermore, the PMOS transistor
38
turns on as its drain voltage rises above Vcc, causing an additional drain-source current to flow. In each case, the effect of the overvoltage on I/O pad
4
is to source current from a device driving the

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