Electronic digital logic circuitry – Signal sensitivity or transmission integrity
Patent
1993-06-07
1995-02-07
Hudspeth, David R.
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
361 91, 326 33, 326 83, H03K 1710
Patent
active
053878264
ABSTRACT:
The present invention provides in some embodiments output buffers and input/output buffers which block the charge leakage from the bus to the internal power supply when the bus voltage exceeds in magnitude the internal power supply voltage or when the module is powered down. This functionality is achieved as follows in some embodiments. A PMOS isolation transistor is connected in series with a pull-up transistor between the internal power supply and the buffer output terminal connected to the bus. The gate of the isolation transistor is connected through a PMOS transistor P to the output terminal and through an NMOS transistor N to ground. The gates of transistors P and N are connected to each other. When the driver is enabled and the pull-up transistor is on, the gates of transistors P and N are high. Transistor P is therefore off. Transistor N is on grounding the gate of the isolation transistor. The isolation transistor turns on allowing the pull-up transistor to drive the output terminal. When the driver is disabled, the gates of transistors P and N are driven low. Transistor N is therefore off. When the voltage on the output terminal is above the absolute value .vertline. VTP.vertline. of the threshold voltage of transistor P, transistor P turns on connecting the output terminal to the gate of the isolation transistor. Thus, if the voltage on the output terminal exceeds in magnitude the internal power supply voltage, the isolation transistor is off because its gate and its drain are connected to the output terminal and are therefore at the same voltage. The backgate of the isolation transistor is connected to the transistor drain and hence the drain/backgate diode is off. The charge leakage is therefore suppressed.
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Article entitled: "Level Transistor Logic with no DC Power Dissipation" published in the International Technology Disclosure Journal 9:06 by author unknown 104279.
Duncan Richard L.
Shay Michael J.
Hudspeth David R.
National Semiconductor Corporation
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