Oversampling data recovery circuit and method for a receiver

Pulse or digital communications – Synchronizers – Synchronizing the sampling time of digital data

Reexamination Certificate

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C375S360000, C375S340000

Reexamination Certificate

active

07936855

ABSTRACT:
An oversampling data recovery circuit for a receiver comprises a plurality of sampling circuits for sampling an input data upon a plurality of clocks to generate a plurality of sample data, respectively, an edge detector for determining an edge of the input data by monitoring the plurality of sample data, and a state machine for selecting one from the plurality of sample data as an output data of the oversampling data recovery circuit according to the edge of the input data, such that the receiver will have an optimum timing margin.

REFERENCES:
patent: 6947493 (2005-09-01), Cohen et al.
patent: 7015726 (2006-03-01), Tayler et al.
patent: 7240249 (2007-07-01), Buchmann et al.
patent: 2003/0068000 (2003-04-01), Warren
patent: 2004/0037383 (2004-02-01), Song
patent: 2006/0044022 (2006-03-01), Tayler et al.

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